ZHCSO15A December 2021 – February 2023 DLPC4420
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 System Oscillators Timing Requirements
- 6.7 Test and Reset Timing Requirements
- 6.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements
- 6.9 Port 1 Input Pixel Timing Requirements
- 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
- 6.11 DMD LVDS Interface Timing Requirements
- 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
- 6.13 Programmable Output Clocks Switching Characteristics
- 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
- 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 85 pF (unless otherwise noted)
| PARAMETER | FROM INPUT | TO OUTPUT | MIN | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tpd | Output Propagation, Clock to Q | TCK↓ | TDO1 | 3 | 12 | ns |
Figure 6-1 System Oscillators
Figure 6-2 Power Up
Figure 6-3 Power Down
Figure 6-4 I/O Boundary Scan
Figure 6-5 Programmable Output Clocks
Figure 6-6 Port1, Port2, and Port3 Input Interface
Figure 6-7 Synchronous Serial Port
Interface—Primary
Figure 6-8 Synchronous Serial Port
Interface—Secondary
Figure 6-9 DMD LVDS Interface