ZHCSO15A December   2021  – February 2023 DLPC4420

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements
    11. 6.11 DMD LVDS Interface Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
      2. 7.3.2 Spread Spectrum Clock Generator Support
      3. 7.3.3 GPIO Interface
      4. 7.3.4 Source Input Blanking
      5. 7.3.5 Video Graphics Processing Delay
      6. 7.3.6 Program Memory Flash/SRAM Interface
      7. 7.3.7 Calibration and Debug Support
      8. 7.3.8 Board Level Test Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC4420 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1V System Power
      3. 9.4.3 1.8V System Power
      4. 9.4.4 3.3V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC4420 Power
      2. 10.1.2 PCB Layout Guidelines for Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 Layout Example
      5. 10.1.5 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 第三方产品免责声明
    2. 11.2 Device Support
      1. 11.2.1 Video Timing Parameter Definitions
      2. 11.2.2 Device Nomenclature
      3. 11.2.3 Device Markings
        1. 11.2.3.1 Device Marking
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 接收文档更新通知
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 静电放电警告
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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6.14 Synchronous Serial Port Interface (SSP) Switching Characteristics

over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 50 pF (unless otherwise noted)
PARAMETERTEST CONDITIONSFROM (INPUT)TO (OUTPUT)MINMAXUNIT
fclockClock Frequency, SSPx_CLKN/ASSPx_CLK7325000kHz
tcCycle time, SSPx_CLKN/ASSPx_CLK0.04013.6µs
tW(H)Pulse Duration, high50% to 50% reference points (signal)N/ASSPx_CLK40%
tW(L)Pulse Duration, low50% to 50% reference points (signal)N/ASSPx_CLK40%
SSP Primary(1)
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↓SSPx_DO-55ns
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↑SSPx_DO-55ns
SSP Secondary(1)
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↓SSPx_DO034ns
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↑SSPx_DO034ns
(1) The SSP can be used as an SSP Primary, or as an SSP Secondary. When used as a Primary, the SSP can be configured to sample DI with the same internal clock edge used to transmit the next DO, which provides a full cycle rather than a half cycle timing path, allowing operation at higher SPI clock frequencies.
(2) The SSP can be configured into four different operational modes/configurations.
Table 6-1 SSP Clock Operational Modes
SPI Clocking ModeSPI Clock Polarity (CPOL)SPI Clock Phase (CPHA)
000
101
210
311