ZHCSLO4D September   2007  – November 2021 DAC5662A

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Resistance Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, AC
    8. 6.8  Electrical Characteristics, DC
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Inputs and Timing
      1. 7.1.1 Digital Inputs
      2. 7.1.2 Input Interfaces
      3. 7.1.3 双总线数据接口和时序
      4. 7.1.4 Single-Bus Interleaved Data Interface and Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Transfer Function
      2. 8.3.2 Analog Outputs
      3. 8.3.3 Output Configurations
      4. 8.3.4 Differential With Transformer
      5. 8.3.5 Single-Ended Configuration
      6. 8.3.6 Reference Operation
        1. 8.3.6.1 Internal Reference
        2. 8.3.6.2 External Reference
      7. 8.3.7 Gain Setting Option
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Informmation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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5 Pin Configurations and Functions

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Table 5-1 Pin Functions
Pin I/O DESCRIPTION
NAME NO.
AGND 38 I Analog ground
AVDD 47 I Analog supply voltage
BIASJ_A 44 O Full-scale output current bias for DACA
BIASJ_B 41 O Full-scale output current bias for DACB
CLKA/CLKIQ 18 I Clock input for DACA, CLKIQ in interleaved mode.
CLKB/RESETIQ 19 I Clock input for DACB, RESETIQ in interleaved mode.
DA[11:0] 1-12 I Data port A. DA11 is MSB and DA0 is LSB. Internal pulldown.
DB[11:0] 23-34 I Data port B. DB11 is MSB and DB0 is LSB. Internal pulldown.
DGND 15, 21 I Digital ground
DVDD 16, 22 I Digital supply voltage
EXTIO 43 I/O Internal reference output (bypass with 0.1 μF to AGND) or external reference input.
GSET 42 I Gain-setting mode: H - 1 resistor, L - 2 resistors. Internal pullup.
IOUTA1 46 O DACA current output. Full-scale with all bits of DA high.
IOUTA2 45 O DACA complementary current output. Full-scale with all bits of DA low.
IOUTB1 39 O DACB current output. Full-scale with all bits of DB high.
IOUTB2 40 O DACB complementary current output. Full-scale with all bits of DB low.
MODE 48 I Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.
NC 13, 14, 35, 36 - No connection
SLEEP 37 I Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode. Internal pulldown.
WRTA/WRTIQ 17 I Input write signal for PORT A (WRTIQ in interleaving mode).
WRTB/SELECTIQ 20 I Input write signal for PORT B (SELECTIQ in interleaving mode).