ZHCSLO4D September 2007 – November 2021 DAC5662A
PRODUCTION DATA
The single carrier signal with an intermediate frequency of 30.72 MHz must be created in the digital processor at a sample rate of 122.88 Msps for DAC. These 12 bit samples are placed on the 12b CMOS input port of the DAC.
A CMOS DAC clock must be generated from a clock source at 122.88 MHz. This must be provided to the CLK pin of the DAC. The IOUTA and IOUTB differential connections must be connected to a transformer to provide a single ended output. A typical 1:1 impedance transformer is used on the device EVM. The DAC5662AEVM provides a good reference for this design example.