ZHCSLO4D September   2007  – November 2021 DAC5662A

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Resistance Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, AC
    8. 6.8  Electrical Characteristics, DC
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Inputs and Timing
      1. 7.1.1 Digital Inputs
      2. 7.1.2 Input Interfaces
      3. 7.1.3 双总线数据接口和时序
      4. 7.1.4 Single-Bus Interleaved Data Interface and Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Transfer Function
      2. 8.3.2 Analog Outputs
      3. 8.3.3 Output Configurations
      4. 8.3.4 Differential With Transformer
      5. 8.3.5 Single-Ended Configuration
      6. 8.3.6 Reference Operation
        1. 8.3.6.1 Internal Reference
        2. 8.3.6.2 External Reference
      7. 8.3.7 Gain Setting Option
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Informmation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.1.1 Digital Inputs

The data input ports of the DAC5662A accept a standard positive coding with data bit D11 being the most significant bit (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best performance will typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their specified limits.

All digital inputs of the DAC5662A are CMOS compatible. Figure 7-1 and Figure 7-2 show schematics of the equivalent CMOS digital inputs of the DAC5662A. The pullup and pulldown circuitry is approximately equivalent to 100kΩ. The 12-bit digital data input follows the offset positive binary coding scheme. The DAC5662A is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.

GUID-290BCE3F-48FC-49FB-9BF7-C9B9E395C77B-low.gifFigure 7-1 CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
GUID-7C61BB61-B0BF-4943-992A-2D75B4DC815D-low.gifFigure 7-2 CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor