ZHCS065G March   2011  – January 2024 DAC3482

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics – DC Specifications
    6. 5.6  Electrical Characteristics – Digital Specifications
    7. 5.7  Electrical Characteristics – AC Specifications
    8. 5.8  Electrical Characteristics - Phase-Locked Loop Specifications
    9. 5.9  Timing Requirements - Digital Specifications
    10. 5.10 Switching Characteristics – AC Specifications
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interface
      2. 6.3.2  Data Interface
        1. 6.3.2.1 Word-Wide Format
        2. 6.3.2.2 Byte-Wide Format
      3. 6.3.3  Input FIFO
      4. 6.3.4  FIFO Modes of Operation
        1. 6.3.4.1 Dual Sync Source Mode
        2. 6.3.4.2 Single Sync Source Mode
        3. 6.3.4.3 Bypass Mode
      5. 6.3.5  Clocking Modes
        1. 6.3.5.1 PLL Bypass Mode
        2. 6.3.5.2 PLL Mode
      6. 6.3.6  FIR Filters
      7. 6.3.7  Complex Signal Mixer
        1. 6.3.7.1 Full Complex Mixer
        2. 6.3.7.2 Coarse Complex Mixer
        3. 6.3.7.3 Mixer Gain
        4. 6.3.7.4 Real Channel Upconversion
      8. 6.3.8  Quadrature Modulation Correction (QMC)
        1. 6.3.8.1 Gain and Phase Correction
        2. 6.3.8.2 Offset Correction
        3. 6.3.8.3 Group Delay Correction
      9. 6.3.9  Temperature Sensor
      10. 6.3.10 Data Pattern Checker
      11. 6.3.11 Parity Check Test
        1. 6.3.11.1 Word-by-Word Parity
        2. 6.3.11.2 Block Parity
      12. 6.3.12 DAC3482 Alarm Monitoring
      13. 6.3.13 LVPECL Inputs
      14. 6.3.14 LVDS Inputs
      15. 6.3.15 Unused LVDS Port Termination
      16. 6.3.16 CMOS Digital Inputs
      17. 6.3.17 Reference Operation
      18. 6.3.18 DAC Transfer Function
      19. 6.3.19 Analog Current Outputs
    4. 6.4 Device Functional Modes
      1. 6.4.1 Multi-Device Synchronization
        1. 6.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 6.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 6.4.1.3 Multi-Device Operation: Single Sync Source Mode
    5. 6.5 Programming
      1. 6.5.1 Power-Up Sequence
      2. 6.5.2 Example Start-Up Routine
        1. 6.5.2.1 Device Configuration
        2. 6.5.2.2 PLL Configuration
        3. 6.5.2.3 NCO Configuration
        4. 6.5.2.4 Example Start-Up Sequence
    6. 6.6 Register Map
      1. 6.6.1 Register Descriptions
        1. 6.6.1.1  Register Name: config0 – Address: 0x00, Default: 0x049C
        2. 6.6.1.2  Register Name: config1 – Address: 0x01, Default: 0x050E
        3. 6.6.1.3  Register Name: config2 – Address: 0x02, Default: 0x7000
        4. 6.6.1.4  Register Name: config3 – Address: 0x03, Default: 0xF000
        5. 6.6.1.5  Register Name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6. 6.6.1.6  Register Name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7. 6.6.1.7  Register Name: config6 – Address: 0x06, Default: No RESET Value (READ ONLY)
        8. 6.6.1.8  Register Name: config7 – Address: 0x07, Default: 0xFFFF
        9. 6.6.1.9  Register Name: config8 – Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. 6.6.1.10 Register Name: config9 – Address: 0x09, Default: 0x8000
        11. 6.6.1.11 Register Name: config10 – Address: 0x0A, Default: 0x0000
        12. 6.6.1.12 Register Name: config11 – Address: 0x0B, Default: 0x0000
        13. 6.6.1.13 Register Name: config12 – Address: 0x0C, Default: 0x0400
        14. 6.6.1.14 Register Name: config13 – Address: 0x0D, Default: 0x0400
        15. 6.6.1.15 Register Name: config14 – Address: 0x0E, Default: 0x0400
        16. 6.6.1.16 Register Name: config15 – Address: 0x0F, Default: 0x0400
        17. 6.6.1.17 Register Name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. 6.6.1.18 Register Name: config17 – Address: 0x11, Default: 0x0000
        19. 6.6.1.19 Register Name: config18 – Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. 6.6.1.20 Register Name: config19 – Address: 0x13, Default: 0x0000
        21. 6.6.1.21 Register Name: config20 – Address: 0x14, Default: 0x0000
        22. 6.6.1.22 Register Name: config21 – Address: 0x15, Default: 0x0000
        23. 6.6.1.23 Register name: config22 – Address: 0x16, Default: 0x0000
        24. 6.6.1.24 Register Name: config23 – Address: 0x17, Default: 0x0000
        25. 6.6.1.25 Register Name: config24 – Address: 0x18, Default: NA
        26. 6.6.1.26 Register Name: config25 – Address: 0x19, Default: 0x0440
        27. 6.6.1.27 Register Name: config26 – Address: 0x1A, Default: 0x0020
        28. 6.6.1.28 Register Name: config27 – Address: 0x1B, Default: 0x0000
        29. 6.6.1.29 Register Name: config28 – Address: 0x1C, Default: 0x0000
        30. 6.6.1.30 Register Name: config29 – Address: 0x1D, Default: 0x0000
        31. 6.6.1.31 Register Name: config30 – Address: 0x1E, Default: 0x1111
        32. 6.6.1.32 Register Name: config31 – Address: 0x1F, Default: 0x1140
        33. 6.6.1.33 Register Name: config32 – Address: 0x20, Default: 0x2400
        34. 6.6.1.34 Register Name: config33 – Address: 0x21, Default: 0x0000
        35. 6.6.1.35 Register Name: config34 – Address: 0x22, Default: 0x1B1B
        36. 6.6.1.36 Register Name: config35 – Address: 0x23, Default: 0xFFFF
        37. 6.6.1.37 Register Name: config36 – Address: 0x24, Default: 0x0000
        38. 6.6.1.38 Register Name: config37 – Address: 0x25, Default: 0x7A7A
        39. 6.6.1.39 Register Name: config38 – Address: 0x26, Default: 0xB6B6
        40. 6.6.1.40 Register Name: config39 – Address: 0x27, Default: 0xEAEA
        41. 6.6.1.41 Register Name: config40 – Address: 0x28, Default: 0x4545
        42. 6.6.1.42 Register Name: config41 – Address: 0x29, Default: 0x1A1A
        43. 6.6.1.43 Register Name: config42 – Address: 0x2A, Default: 0x1616
        44. 6.6.1.44 Register Name: config43 – Address: 0x2B, Default: 0xAAAA
        45. 6.6.1.45 Register Name: config44 – Address: 0x2C, Default: 0xC6C6
        46. 6.6.1.46 Register Name: config45 – Address: 0x2D, Default: 0x0004
        47. 6.6.1.47 Register Name: config46 – Address: 0x2E, Default: 0x0000
        48. 6.6.1.48 Register Name: config47 – Address: 0x2F, Default: 0x0000
        49. 6.6.1.49 Register Name: config48 – Address: 0x30, Default: 0x0000
        50. 6.6.1.50 Register Name: version– Address: 0x7F, Default: 0x540C (READ ONLY)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 IF Based LTE Transmitter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Data Input Rate
          2. 7.2.1.2.2 Interpolation
          3. 7.2.1.2.3 LO Feedthrough and Sideband Correction
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Data Input Rate
          2. 7.2.2.2.2 Interpolation
          3. 7.2.2.2.3 LO Feedthrough and Sideband Correction
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
      3. 7.4.3 Assembly
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
        1. 8.1.1.1 Definition of Specifications
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

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6.6 Register Map

Table 6-11 Register Map(1)
NameAddressDefault(MSB)
Bit 15		Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1(LSB)
Bit 0
config00x000x049Cqmc_offset_ enareservedqmc_corr_ enareservedinterp(3:0)fifo_enareservedreservedalarm_out_ enaalarm_outpolclkdiv_sync_ enainvsinc_enareserved
config10x010x050Eiotest_enareservedreserved64cnt_
ena		oddeven_parityword_
parity_
ena		frame_
parity_e
na		reservedreserveddacI_ complementdacQ_ complementreservedalarm_
2away_
ena		alarm_
1away_
ena		alarm_
collision_
ena		reserved
config20x020x700016bit_indacclk gone_enadataclk gone_enacollision_ gone_enaresrevedreservedreservedreservedsif4_enamixer_enamixer_gainnco_enarevbusreservedtwosreserved
config30x030xF000coarse_dac(3:0)reservedreservedsif_txenable
config40x04NAiotest_results(15:0)
config50x05NAalarm_
from_
zerochk		reservedalarms_from_fifo(2:0)alarm_ dacclk_
gone		alarm_ dataclk_
gone		alarm_
output_
gone		alarm_
from _
iotest		reservedalarm_ from_pllalarm_ rparityalarm_
fparity		alarm_ frame_parityreservedreserved
config60x06NAtempdata(7:0)reservedreservedreserved
config70x070xFFFFalarms_mask(15:0)
config80x080x0000reservedreservedreservedqmc_offsetI(12:0)
config90x090x8000fifo_offset(2:0)qmc_offsetQ(12:0)
config100x0A0x0000reservedreservedreservedreserved
config110x0B0x0000reservedreservedreservedreserved
config120x0C0x0400reservedreservedreservedreservedreservedqmc_gainI(10:0)
config130x0D0x0400cmix(3:0)reservedqmc_gainQ(10:0)
config140x0E0x0400reservedreservedreservedreservedreservedreserved
config150x0F0x0400output_delay (1:0)reservedreservedreserved
config160x100x0000reservedreservedreservedreservedqmc_phase(11:0)
config170x110x0000reservedreservedreservedreservedreserved
config180x120x0000phase_offset(15:0)
config190x130x0000reserved
config200x140x0000phase_add(15:0)
config210x150x0000phase_add(31:16)
config220x160x0000reserved
config230x170x0000reserved
config240x18NAreservedpll_resetpll_ ndivsync_ enapll_enareservedpll_cp(1:0)pll_p(2:0)pll_lfvolt(2:0)
config250x190x0440pll_m(7:0)pll_n(3:0)pll_vcoitune(2:0)reserved
config260x1A0x0020pll_vco(5:0)reservedreservedbias_
sleep		tsense_
sleep		pll_sleepclkrecv_
sleep		reservedreservedreservedreserved
config270x1B0x0000extref_enareservedreservedreservedfuse_
sleep		reservedreservedreservedreservedreservedreserved
config280x1C0x0000reservedreserved
config290x1D0x0000reservedreserved
config300x1E0x1111syncsel_qmoffset(3:0)reservedsyncsel_qmcorr(3:0)reserved
config310x1F0x1140syncsel_mixer(3:0)reservedsyncsel_nco(3:0)syncsel_dataformattersif_syncreserved
config320x200x2400syncsel_fifoin(3:0)syncsel_fifoout(3:0)reservedclkdiv_ sync_sel
config330x210x0000reserved
config340x220x1B1Breservedreservedreservedreservedreservedreservedreservedreserved
config350x230xFFFFsleep_cntl(15:0)
config360x240x0000datadly(2:0)clkdly(2:0)reserved
config370x250x7A7Aiotest_pattern0
config380x260xB6B6iotest_pattern1
config390x270xEAEAiotest_pattern2
config400x280x4545iotest_pattern3
config410x290x1A1Aiotest_pattern4
config420x2A0x1616iotest_pattern5
config430x2B0xAAAAiotest_pattern6
config440x2C0xC6C6iotest_pattern7
config450x2D0x0004reservedostrtodig_selramp_enareservedsifdac_ena
config460x2E0x0000reservedgrp_delayI(7:0)
config470x2F0x0000grp_delayQ(7:0)reserved
config480x300x0000sifdac(15:0)
version0x7F0x540Creservedreservedreservedreserveddeviceid(1:0)versionid(2:0)
(1) Unless otherwise noted, all reserved registers should be programmed to default values.