Typical values stated where TA = 25°C and VBAT = 55.0 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 55 V (unless otherwise noted)
||Internal cell balancing resistance(1)
||RDS(ON) for internal FET switch at VVC(n) - VVC(n-1) = 1.5V, 1 ≤ n ≤ 10, VBAT ≥ 4.7 V
(1) Cell balancing must be controlled to limit the current based on the absolute maximum allowed current, and to avoid exceeding the recommended device operating temperature. This can be accomplished by appropriate sizing of the offchip cell input resistors and limiting the number of cells that can be balanced simultaneously.