ZHCSKO3B January   2020  – September 2020 BQ25611D

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-On-Reset (POR)
      2. 9.3.2  Device Power Up from Battery without Input Source
      3. 9.3.3  Power Up from Input Source
        1. 9.3.3.1 Power Up REGN LDO
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 9.3.3.3.1 D+/D– Detection Sets Input Current Limit
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Power Up Converter in Buck Mode
        6. 9.3.3.6 HIZ Mode with Adapter Present
      4. 9.3.4  Boost Mode Operation From Battery
      5. 9.3.5  Power Path Management
        1. 9.3.5.1 Narrow VDC Architecture
        2. 9.3.5.2 Dynamic Power Management
        3. 9.3.5.3 Supplement Mode
      6. 9.3.6  Battery Charging Management
        1. 9.3.6.1 Autonomous Charging Cycle
        2. 9.3.6.2 Battery Charging Profile
        3. 9.3.6.3 Charging Termination
        4. 9.3.6.4 Thermistor Qualification
          1. 9.3.6.4.1 JEITA Guideline Compliance During Charging Mode
          2. 9.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 9.3.6.5 Charging Safety Timer
      7. 9.3.7  Ship Mode and QON Pin
        1. 9.3.7.1 BATFET Disable (Enter Ship Mode)
        2. 9.3.7.2 BATFET Enable (Exit Ship Mode)
        3. 9.3.7.3 BATFET Full System Reset
      8. 9.3.8  Status Outputs ( STAT, INT )
        1. 9.3.8.1 Charging Status Indicator (STAT)
        2. 9.3.8.2 Interrupt to Host ( INT)
      9. 9.3.9  Protections
        1. 9.3.9.1 Voltage and Current Monitoring in Buck Mode
          1. 9.3.9.1.1 Input Over-Voltage Protection (ACOV)
          2. 9.3.9.1.2 System Over-Voltage Protection (SYSOVP)
        2. 9.3.9.2 Voltage and Current Monitoring in Boost Mode
          1. 9.3.9.2.1 Boost Mode Over-Voltage Protection
        3. 9.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 9.3.9.3.1 Thermal Protection in Buck Mode
          2. 9.3.9.3.2 Thermal Protection in Boost Mode
        4. 9.3.9.4 Battery Protection
          1. 9.3.9.4.1 Battery Over-Voltage Protection (BATOVP)
          2. 9.3.9.4.2 Battery Over-Discharge Protection
          3. 9.3.9.4.3 System Over-Current Protection
      10. 9.3.10 Serial Interface
        1. 9.3.10.1 Data Validity
        2. 9.3.10.2 START and STOP Conditions
        3. 9.3.10.3 Byte Format
        4. 9.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.10.5 Slave Address and Data Direction Bit
        6. 9.3.10.6 Single Read and Write
        7. 9.3.10.7 Multi-Read and Multi-Write
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
    5. 9.5 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor and Resistor
        3. 10.2.2.3 Output Capacitor
    3. 10.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
BAT 13 P Battery connection point to the positive terminal of the battery pack. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF(2) closely to the BAT pin.
14
BATSNS 10 AI Battery voltage sensing pin for charge voltage regulation. In order to minimize the parasitic trace resistance during charging, BATSNS pin is connected to the positive terminal of battery pack as close as possible. If BATSNS pin is open or short to ground, BATSNS_STAT bit is set to 1 and charger regulates the battery voltage through BAT pin.
BTST 21 P PWM high side driver positive supply. Internally, the BTST is connected to the cathode of the boot-strap diode. Connect the 0.047-μF bootstrap capacitor(2) from SW to BTST.
CE 9 DI Charge enable pin. When this pin is driven LOW, battery charging is enabled.
D+ 2 AIO Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors.
D- 3 AIO Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2 and nonstandard adaptors.
GND 17 — Ground.
18
INT 7 DO Open-drain interrupt output. Connect the INT to a logic rail through a 10-kΩ resistor. The INT pin sends an active low, 256-µs pulse to the host to report charger device status and fault.
NC 8 — Not connected.
PMID 23 P Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. Place a 10-µF capacitor(2) on PMID to GND.
QON 12 DI BATFET enable/reset control input. When the BATFET is in ship mode, a logic LOW of tSHIPMODE duration turns on BATFET to exit ship mode. When the BATFET is not in ship mode, a logic LOW of tQON_RST (minimum 8 s) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enables BATFET to provide full system power reset. The host chooses the BATFET reset function with VBUS unplugged or not through I2C bit BATFET_RST_WVBUS. The pin is pulled up to VQON through 200 kΩ to maintain default HIGH logic during ship mode. It has an internal clamp to 6.5 V. QON pin is pulled through 200-kΩ resistor to VQON. VQON is supplied from VBUS minus 2 diode voltage drop or from VBAT minus 1 diode voltage drop. It has an internal voltage clamp to 6.5 V.
REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the anode of the boot-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor(2) from REGN to analog GND. The capacitor should be placed close to the IC.
SCL 5 DI I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA 6 DIO I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
STAT 4 DO Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor. The STAT pin indicates charger status.
Charge in progress: LOW.
Charge complete or charger in SLEEP mode: HIGH.
Charge suspend (fault response): blink at 1 Hz.
SW 19 P Switching node connecting to output inductor. Internally, SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF bootstrap capacitor(2) from SW to BTST.
20
SYS 15 P System output connection point. The internal current sensing resistor is connected between SYS and BAT. Connect a 10 µF (min)(2) closely to the SYS pin.
16
TS 11 AI Battery temperature qualification voltage input. Connect a negative temperature coefficient thermistor (NTC). Program temperature window with a resistor divider from REGN to TS to GND. Charge and boost mode suspended when TS pin voltage is out of range. When TS pin is not used, connect a 10-kΩ resistor from REGN to TS and a 10-kΩ resistor from TS to GND or set TS_IGNORE to HIGH to ignore TS pin. It is recommended to use a 103AT-2 thermistor.
VAC 1 P Input voltage sensing. This pin must be tied to VBUS.
VBUS 24 P Charger input voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-uF ceramic capacitor(2) from VBUS to GND and place it as close as possible to the device.
Thermal Pad — P Ground reference for the device that is also the thermal pad used to conduct heat from the device. This connection serves two purposes. The first purpose is to provide an electrical ground connection for the device. The second purpose is to provide a low thermal-impedance path from the device die to the PCB. This pad should be tied externally to a ground plane.
(1) AI = Analog Input, AO = Analog Output, AIO = Analog Input Output, DI = Digital input, DO = Digital Output, DIO = Digital Input Output, P = Power
(2) All capacitors are ceramic unless otherwise specified