ZHCSKO3B January   2020  – September 2020 BQ25611D

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-On-Reset (POR)
      2. 9.3.2  Device Power Up from Battery without Input Source
      3. 9.3.3  Power Up from Input Source
        1. 9.3.3.1 Power Up REGN LDO
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 9.3.3.3.1 D+/D– Detection Sets Input Current Limit
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Power Up Converter in Buck Mode
        6. 9.3.3.6 HIZ Mode with Adapter Present
      4. 9.3.4  Boost Mode Operation From Battery
      5. 9.3.5  Power Path Management
        1. 9.3.5.1 Narrow VDC Architecture
        2. 9.3.5.2 Dynamic Power Management
        3. 9.3.5.3 Supplement Mode
      6. 9.3.6  Battery Charging Management
        1. 9.3.6.1 Autonomous Charging Cycle
        2. 9.3.6.2 Battery Charging Profile
        3. 9.3.6.3 Charging Termination
        4. 9.3.6.4 Thermistor Qualification
          1. 9.3.6.4.1 JEITA Guideline Compliance During Charging Mode
          2. 9.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 9.3.6.5 Charging Safety Timer
      7. 9.3.7  Ship Mode and QON Pin
        1. 9.3.7.1 BATFET Disable (Enter Ship Mode)
        2. 9.3.7.2 BATFET Enable (Exit Ship Mode)
        3. 9.3.7.3 BATFET Full System Reset
      8. 9.3.8  Status Outputs ( STAT, INT )
        1. 9.3.8.1 Charging Status Indicator (STAT)
        2. 9.3.8.2 Interrupt to Host ( INT)
      9. 9.3.9  Protections
        1. 9.3.9.1 Voltage and Current Monitoring in Buck Mode
          1. 9.3.9.1.1 Input Over-Voltage Protection (ACOV)
          2. 9.3.9.1.2 System Over-Voltage Protection (SYSOVP)
        2. 9.3.9.2 Voltage and Current Monitoring in Boost Mode
          1. 9.3.9.2.1 Boost Mode Over-Voltage Protection
        3. 9.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 9.3.9.3.1 Thermal Protection in Buck Mode
          2. 9.3.9.3.2 Thermal Protection in Boost Mode
        4. 9.3.9.4 Battery Protection
          1. 9.3.9.4.1 Battery Over-Voltage Protection (BATOVP)
          2. 9.3.9.4.2 Battery Over-Discharge Protection
          3. 9.3.9.4.3 System Over-Current Protection
      10. 9.3.10 Serial Interface
        1. 9.3.10.1 Data Validity
        2. 9.3.10.2 START and STOP Conditions
        3. 9.3.10.3 Byte Format
        4. 9.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.10.5 Slave Address and Data Direction Bit
        6. 9.3.10.6 Single Read and Write
        7. 9.3.10.7 Multi-Read and Multi-Write
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
    5. 9.5 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor and Resistor
        3. 10.2.2.3 Output Capacitor
    3. 10.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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9.5 Register Maps

I2C Slave Address: 6BH

Default I2C Slave Address: 0x6B (1101 011B + R/ W)

Table 9-6 I2C Registers
Address Access Type Acronym Register Name Section
00h R/W REG00 Input Current Limit Go
01h R/W REG01 Charger Control 0 Go
02h R/W REG02 Charge Current Limit Go
03h R/W REG03 pre-charge and Termination Current Limit Go
04h R/W REG04 Battery Voltage Limit Go
05h R/W REG05 Charger Control 1 Go
06h R/W REG06 Charger Control 2 Go
07h R/W REG07 Charger Control 3 Go
08h R REG08 Charger Status 0 Go
09h R REG09 Charger Status 1 Go
0Ah R REG0A Charger Status 2 Go
0Bh R REG0B Part Information Go
0Ch R/W REG0C Charger Control 4 Go

Complex bit access types are encoded to fit into small table cells. Table 9-7 shows the codes that are used for access types in this section.

Table 9-7 I2C Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset Value
-nValue after reset
-XUndefined value

9.5.1 Input Current Limit Register (Address = 00h) [reset = 17h]

Figure 9-17 REG00 Register
7 6 5 4 3 2 1 0
0 0 0 1 0 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-8 REG00 Field Descriptions
BitFieldPORTypeResetDescription
7EN_HIZ0R/Wby REG_RST
by Watchdog		HIZ mode enable in buck mode.
0 – Disable (default)
1 – Enable
6TS_IGNORE0R/Wby REG_RSTWhen charger does not monitor the NTC, host sets this bit to 1 to ignore the TS pin condition during charging and boost mode.
0 – Include TS pin into charge and boost mode enable conditions. (default)
1 – Ignore TS pin. Always consider TS is good to allow charging and boost mode. NTC_FAULT bits are 000 to report normal status.
5BATSNS_DIS0R/Wby REG_RSTSelect either BATSNS pin or BAT pin to regulate battery voltage.
0 – Enable BATSNS in battery CV regulation. If the device fails BATSNS open/short detection (BATSNS_STAT = 1). Battery voltage is regulated through BAT pin. (default)
1 – Disable BATSNS. Use BAT pin in battery CV regulation.
4IINDPM[4]1R/Wby REG_RST1600 mAInput current limit setting (maximum limit, not typical)
Offset: 100 mA
Range: 100 mA (000000) – 3.2 A (11111)
Default: 2400 mA (10111)
IINDPM bits are changed automatically after Onput Source Type Detection (IINDPM Threshold) is completed
USB SDP = 500 mA
USB CDP = 1.5 A
USB DCP = 2.4 A
Unknown Adapter = 500 mA
Non-Standard Adapter = 1 A, 2 A, 2.1 A, or 2.4
Host can reprogram IINDPM register bits after input source detection is completed.
3IINDPM[3]0R/Wby REG_RST800 mA
2IINDPM[2]1R/Wby REG_RST400 mA
1IINDPM[1]1R/Wby REG_RST200 mA
0IINDPM[0]1R/Wby REG_RST100 mA
LEGEND: R/W = Read/Write; R = Read only

9.5.2 Charger Control 0 Register (Address = 01h) [reset = 1Ah]

Figure 9-18 REG01 Register
7 6 5 4 3 2 1 0
0 0 0 1 1 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-9 REG01 Field Descriptions
BitFieldPORTypeResetDescription
7PFM_DIS0R/Wby REG_RSTPFM disable in both buck and boost mode.
0 – PFM enable (default)
1 – PFM disable
6WD_RST0R/Wby REG_RST
by Watchdog		I2C Watchdog timer reset. Back to 0 after watchdog timer reset
0 – Normal (default)
1 – Reset
5BST_CONFIG0R/Wby REG_RST
by Watchdog		Boost mode enable. In charging case application, based on adapter plug-in or removal, the charger will automatically transit between charging mode and boost mode by setting BST_CONFIG bit and CHG_CONFIG bit both to 1.
0 – Boost mode disable (default)
1 – Boost mode enable
4CHG_CONFIG1R/Wby REG_RST
by Watchdog		Battery charging buck mode enable. Charging is enabled when CE pin is pulled low, CHG_CONFIG bit is 1 and charge current is not zero.
0 – Charge Disable
1 – Charge Enable (default)
3SYS_MIN[2]1R/Wby REG_RSTSystem minimum voltage setting.
000 – 2.6 V
001 – 2.8 V
010 – 3 V
011 – 3.2 V
100 – 3.4 V
101 – 3.5 V (default)
110 – 3.6 V
111 – 3.7 V
2SYS_MIN[1]0R/Wby REG_RST
1SYS_MIN[0]1R/Wby REG_RST
0MIN_VBAT_SEL0R/Wby REG_RSTMinimum battery voltage when exiting boost mode. The rising threshold allows the device to start boost mode if other conditions are valid.
0 – 2.8V VBAT falling, 3 V rising (default)
1 – 2.5V VBAT falling, 2.8V rising
LEGEND: R/W = Read/Write; R = Read only

9.5.3 Charge Current Limit Register (Address = 02h) [reset = 91h]

Figure 9-19 REG02 Register
7 6 5 4 3 2 1 0
1 0 0 1 0 0 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-10 REG02 Field Descriptions
BitFieldPORTypeResetDescription
7BOOST_LIM1R/Wby REG_RST
by Watchdog		Boost mode current regulation limit (minimum current limit, not typical).
0 – 0.5 A
1 – 1.2 A (default)
6Q1_FULLON0R/Wby REG_RSTIn buck mode, charger will fully turn on Q1 RBFET according to this bit setting when IINDPM is below 700 mA. When IINDPM is over 700 mA, Q1 is always fully on. In boost mode , Q1 is always fully on too, regardless of this bit setting.
0 – Partially turn on Q1 for better regulation accuracy when IINDPM is below 700 mA. (default)
1 – Fully turn on Q1 for better efficiency when IINDPM is below 700 mA.
5ICHG[5]0R/Wby REG_RST
by Watchdog		1920 mA Fast charge current setting
Default: 1020 mA (010001)
Range: 0 mA (0000000) – 3000 mA (110010)
ICHG 0 mA disables charge.
ICHG > 3000 mA is clamped to 3000 mA (110010)
4ICHG[4]1R/Wby REG_RST
by Watchdog		960 mA
3ICHG[3]0R/Wby REG_RST
by Watchdog		480 mA
2ICHG[2]0R/Wby REG_RST
by Watchdog		240 mA
1ICHG[1]0R/Wby REG_RST
by Watchdog		120 mA
0ICHG[0]1R/Wby REG_RST
by Watchdog		60 mA
LEGEND: R/W = Read/Write; R = Read only

9.5.4 Pre-charge and Termination Current Limit Register (Address = 03h) [reset = 12h]

Figure 9-20 REG03 Register
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-11 REG03 Field Descriptions
BitFieldPORTypeResetDescription
7IPRECHG[3]0R/Wby REG_RST
by Watchdog		480 mA Pre-charge current setting
Default: 180 mA (0010)
Range: 60 mA (0000) – 780 mA (1100)
Offset: 60 mA
Note: IPRECHG > 780 mA is clamped to 780 mA (1100)
6IPRECHG[2]0R/Wby REG_RST
by Watchdog		240 mA
5IPRECHG[1]1R/Wby REG_RST
by Watchdog		120 mA
4IPRECHG[0]0R/Wby REG_RST
by Watchdog		60 mA
3ITERM[3]0R/Wby REG_RST
by Watchdog		480 mA Termination current setting
Default: 180 mA (0010)
Range: 60 mA – 780 mA (1100)
Offset: 60 mA
2ITERM[2]0R/Wby REG_RST
by Watchdog		240 mA
1ITERM[1]1R/Wby REG_RST
by Watchdog		120 mA
0ITERM[0]0R/Wby REG_RST
by Watchdog		60 mA
LEGEND: R/W = Read/Write; R = Read only

9.5.5 Battery Voltage Limit Register (Address = 04h) [reset = 40h]

Figure 9-21 REG04 Register
7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-12 REG04 Field Descriptions
BitFieldPORTypeResetDescription
7VBATREG[4]0R/Wby REG_RST
by Watchdog		Battery voltage setting, also called VREG.
Default: 4.190 V (01000)
00000 – 3.494 V
00001 – 3.590 V
00010 – 3.686 V
00011 – 3.790 V
00100 – 3.894 V
00101 – 3.990 V
00110 – 4.090 V
00111 – 4.140 V
01000 – 4.190 V
01001 - 11111 – 4.290 V - 4.510 V, 10 mV/step
01110 4.340 V, 10011 4.390V, 11000 4.440 V, 11101 4.490 V
6VBATREG[3]1R/Wby REG_RST
by Watchdog
5VBATREG[2]0R/Wby REG_RST
by Watchdog
4VBATREG[1]0R/Wby REG_RST
by Watchdog
3VBATREG[0]0R/Wby REG_RST
by Watchdog
2TOPOFF_TIMER[1]0R/Wby REG_RST
by Watchdog		Top-off timer setting.
00 – Disabled (Default)
01 – 15 minutes
10 – 30 minutes
11 – 45 minutes
1TOPOFF_TIMER[0]0R/Wby REG_RST
by Watchdog
0VRECHG0R/Wby REG_RST
by Watchdog		Battery recharge threshold setting.
0 – 120 mV (default)
1 – 210 mV
LEGEND: R/W = Read/Write; R = Read only

9.5.6 Charger Control 1 Register (Address = 05h) [reset = 9Eh]

Figure 9-22 REG05 Register
7 6 5 4 3 2 1 0
1 0 0 1 1 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-13 REG05 Field Descriptions
BitFieldPORTypeResetDescription
7EN_TERM1R/Wby REG_RST
by Watchdog		Battery charging termination enable.
0 – Disable
1 – Enable (default)
6 Reserved0R/Wby REG_RST
by Watchdog		 Reserved
5WATCHDOG[1]0R/Wby REG_RST
by Watchdog		Watchdog timer setting.
00 – Disable timer
01 – 40 s (default)
10 – 80 s
11 – 160 s
4WATCHDOG[0]1R/Wby REG_RST
by Watchdog
3EN_TIMER1R/Wby REG_RST
by Watchdog		Battery charging safety timer enable, including both fast charge and pre-charge timers. Pre-charge timer is 2 hours. Fast charge timer is set by REG05[2]
0 – Disable
1 – Enable timer (default)
2CHG_TIMER1R/Wby REG_RST
by Watchdog		Battery fast charging safety timer setting.
0 – 20 hrs
1 – 10 hrs (default)
1TREG1R/Wby REG_RST
by Watchdog		Thermal Regulation Threshold:
0 – 90°C
1 – 110°C (default)
0JEITA_VSET (45C-60C)0R/Wby REG_RST
by Watchdog		Battery voltage setting during JEITA warm (T3 - T5, typically 45C - 60C)
0 – Set Charge Voltage to 4.1 V (max) (default)
1 – Set Charge Voltage to VREG
LEGEND: R/W = Read/Write; R = Read only

9.5.7 Charger Control 2 Register (Address = 06h) [reset = E6h]

Figure 9-23 REG06 Register
7 6 5 4 3 2 1 0
1 1 1 0 0 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-14 REG06 Field Descriptions
BitFieldPORTypeResetDescription
7OVP[1]1R/Wby REG_RSTVACOV threshold during buck mode and boost mode.
00 – 5.85 V
01 – 6.4 V (5-V input)
10 – 11 V (9-V input)
11 – 14.2 V (12-V input) (default)
6OVP[0]1R/Wby REG_RST
5BOOSTV[1]1R/Wby REG_RSTBoost regulation voltage setting
00 – 4.6 V
01 – 4.75 V
10 – 5.0 V (default)
11 – 5.15 V
4BOOSTV[0]0R/Wby REG_RST
3VINDPM[3]0R/Wby REG_RST800 mVVINDPM threshold setting
Default: 4.5 V (0110)
Range: 3.9 V (0000) – 5.4 V (1111)
Offset: 3.9 V
2VINDPM[2]1R/Wby REG_RST400 mV
1VINDPM[1]1R/Wby REG_RST200 mV
0VINDPM[0]0R/Wby REG_RST100 mV
LEGEND: R/W = Read/Write; R = Read only

9.5.8 Charger Control 3 Register (Address = 07h) [reset = 4Ch]

Figure 9-24 REG07 Register
7 6 5 4 3 2 1 0
0 1 0 0 1 1 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-15 REG07 Field Descriptions
BitFieldPORTypeResetDescription
7IINDET_EN0R/Wby REG_RST
by Watchdog		Force input source type detection. After the detection is complete, this bit returns to 0.
0 – Not in input current limit detection. (default)
1 – Force input current limit detection when adapter is present.
6TMR2X_EN1R/Wby REG_RST
by Watchdog		Safety timer is slowed by 2X during input DPM, JEITA cool/warm or thermal regulation.
0 – Disable. Safety timer duration is set by REG05[2].
1 – Safety timer slowed by 2X during input DPM (both V and I) or JEITA cool/warm (except ICHG=100%), or thermal regulation. (default)
5BATFET_DIS0R/Wby REG_RSTBATFET Q4 ON/OFF control. Set this bit to 1 to enter ship mode. To reset the device with adapter present, the host shall set BATFET_RST_WVBUS to 1 and then BATFET_DIS to 1.
0 – Turn on Q4. (default)
1 – Turn off Q4 after tBATFET_DLY delay time (REG07[3])
4BATFET_RST_WVBUS0R/Wby REG_RSTStart BATFET full system reset with or without adapter present.
0 – Start BATFET full system reset after adapter is removed from VBUS. (default)
1 – Start BATFET full system reset when adapter is present on VBUS.
3BATFET_DLY1R/Wby REG_RSTDelay from BATFET_DIS (REG07[5]) set to 1 to BATFET turn off during ship mode.
0 – Turn off BATFET immediately when BATFET_DIS bit is set.
1 – Turn off BATFET after tBATFET_DLY (typ 10 s) when BATFET_DIS bit is set. (default)
2BATFET_RST_EN1R/Wby REG_RST
by Watchdog		Enable BATFET full system reset. The time to start of BATFET full system reset is based on the setting of BATFET_RST_WVBUS bit.
0 – Disable BATFET reset function
1 – Enable BATFET reset function when REG07[5] is also 1. (default)
1VINDPM_BAT_TRACK[1]0R/Wby REG_RSTSets VINDPM to track BAT voltage. Actual VINDPM is higher of register value and VBAT + VINDPM_BAT_TRACK.
00 – Disable function (VINDPM set by register) (default)
01 – VBAT + 200 mV
10 – VBAT + 250 mV
11 – VBAT + 300 mV
0VINDPM_BAT_TRACK[0]0R/Wby REG_RST
LEGEND: R/W = Read/Write; R = Read only

9.5.9 Charger Status 0 Register (Address = 08h)

Figure 9-25 REG08
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-16 REG08 Field Descriptions
BitFieldPORTypeResetDescription
7VBUS_STAT[2]xRNAVBUS Status register

Software current limit is reported in IINDPM register
6VBUS_STAT[1]xRNA
5VBUS_STAT[0]xRNA
4CHRG_STAT[1]xRNACharging status:
00 – Not Charging
01 – Pre-charge or trickle charge (< VBATLOWV)
10 – Fast Charging
11 – Charge Termination
3CHRG_STAT[0]xRNA
2ReservedxRNA Reserved
1THERM_STATxRNA0 – Not in thermal regulation
1 – In thermal regulation
0VSYS_STATxRNA0 – Not in SYS_MIN regulation (VBAT > VSYS_MIN)
1 – In SYS_MIN regulation (VBAT < VSYS_MIN)
LEGEND: R/W = Read/Write; R = Read only

9.5.10 Charger Status 1 Register (Address = 09h)

Figure 9-26 REG09 Register
7 6 5 4 3 2 1 0
1 x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-17 REG09 Field Descriptions
BitFieldPORTypeResetDescription
7WATCHDOG_FAULT1RNA0 – Normal, device is in host mode,
1 – Watchdog timer expiration, device is in default mode.
6BOOST_FAULTxRNA0 – Normal
1 – Fault detected in boost mode (any conditions that are not valid for boost operation), including VBUS overloaded (BST_OVP) or battery is too low (BST_BAT)
5CHRG_FAULT[1]xRNA00 – Normal
01 – Input fault
10 – Thermal shutdown
11 – Charge safety timer expiration
4CHRG_FAULT[0]xRNA
3BAT_FAULTxRNA0 – Normal,
1 – Battery over voltage.
2NTC_FAULT[2]xRNATS fault in buck mode
000 – Normal
010 – Warm
011 – Cool
101 – Cold
110 – Hot
TS fault in boost mode
000 – Normal
101 – Cold
110 – Hot
1NTC_FAULT[1]xRNA
0NTC_FAULT[0]xRNA
LEGEND: R/W = Read/Write; R = Read only

9.5.11 Charger Status 2 Register (Address = 0Ah)

Figure 9-27 REG0A Register
7 6 5 4 3 2 1 0
x x x x x x 0 0
R R R R R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-18 REG0A Field Descriptions
BitFieldPORTypeResetDescription
7VBUS_GDxRNA0 – VBUS does not pass poor source detection
1 – VBUS passes poor source detection
6VINDPM_STATxRNA0 – Not in VINDPM
1 – In VINDPM
5IINDPM_STATxRNA0 – Not in IINDPM
1 – In IINDPM
4BATSNS_STATxRNA0 – BATSNS pin is in good connection. Regulation battery voltage through BATSNS pin.
1 – BATSNS pin is open/short. Regulate battery voltage through BAT pin.
3TOPOFF_ACTIVExRNA0 – Top off timer not counting.
1 – Top off timer counting
2ACOV_STATxRNA0 – Not in ACOV
1 – In ACOV
1VINDPM_INT_ MASK0R/Wby REG_RSTAllow or block INT pulse assertion to host during VINDPM.
0 – INT is asserted to host during VINDPM (default)
1 – No INT pulse asserted to host during VINDPM
0IINDPM_INT_ MASK0R/Wby REG_RSTAllow or block INT pulse assertion to host during IINDPM
0 – INT is asserted to host during IINDPM (default)
1 – No INT pulse asserted to host during IINDPM
LEGEND: R/W = Read/Write; R = Read only

9.5.12 Part Information Register (Address = 0Bh)

Figure 9-28 REG0B Register
7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 0
R/W R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-19 REG0B Field Descriptions
BitFieldPORTypeResetDescription
7REG_RST0R/WNARegister reset
0 – Keep current register setting (default)
1 – Reset to default register value and reset safety timer. This bit returns to 0 after register reset is completed.
6PN[3]1RNABQ25611D: 1010
5PN[2]0RNA
4PN[1]1RNA
3PN[0]0RNA
2
Reserved		1RNAReserved
1
Reserved		0RNAReserved
0
Reserved		0RNA
LEGEND: R/W = Read/Write; R = Read only

9.5.13 Charger Control 4 Register (Address = 0Ch) [reset = 75h]

Figure 9-29 REG0C
7 6 5 4 3 2 1 0
0 1 1 1 0 1 0 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-20 REG0C Field Descriptions
BitFieldPORTypeResetDescription
7JEITA_COOL_ISET [1]0R/Wby REG_RST
by Watchdog		Fast charge current setting during cool temperature range (T1 - T2), as percentage of ICHG in REG02[5:0].
00 – No Charge
01 – 20% of ICHG (default)
10 – 50% of ICHG
11 – 100% of ICHG (safety timer does not become 2X)
6JEITA_COOL_ISET [0]1R/Wby REG_RST
by Watchdog
5JEITA_WARM_ISET [1]1R/Wby REG_RST
by Watchdog		Fast charge current setting during warm temperature range (T3 - T5), as percentage of ICHG in REG02[5:0].
00 – No Charge
01 – 20% of ICHG
10 – 50% of ICHG
11 – 100% of ICHG (safety timer does not become 2X) (default)
4JEITA_WARM_ISET [0]1R/Wby REG_RST
by Watchdog
3JEITA_VT2 [1]0R/Wby REG_RST
by Watchdog		00 – VT2% = 70.75% (5.5°C)
01 – VT2% = 68.25% (10°C) (default)
10 – VT2% = 65.25% (15°C)
11 – VT2% = 62.25% (20°C)
2JEITA_VT2 [0]1R/Wby REG_RST
by Watchdog
1JEITA_VT3 [1]0R/Wby REG_RST
by Watchdog		00 – VT3% = 48.25% (40°C)
01 – VT3% = 44.75% (44.5°C) (default)
10 – VT3% = 40.75% (50.5°C)
11 – VT3% = 37.75% (54.5°C)
0JEITA_VT3 [0]1R/Wby REG_RST
by Watchdog
LEGEND: R/W = Read/Write; R = Read only