ZHCSKO3B January   2020  – September 2020 BQ25611D

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-On-Reset (POR)
      2. 9.3.2  Device Power Up from Battery without Input Source
      3. 9.3.3  Power Up from Input Source
        1. 9.3.3.1 Power Up REGN LDO
        2. 9.3.3.2 Poor Source Qualification
        3. 9.3.3.3 Input Source Type Detection (IINDPM Threshold)
          1. 9.3.3.3.1 D+/D– Detection Sets Input Current Limit
        4. 9.3.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 9.3.3.5 Power Up Converter in Buck Mode
        6. 9.3.3.6 HIZ Mode with Adapter Present
      4. 9.3.4  Boost Mode Operation From Battery
      5. 9.3.5  Power Path Management
        1. 9.3.5.1 Narrow VDC Architecture
        2. 9.3.5.2 Dynamic Power Management
        3. 9.3.5.3 Supplement Mode
      6. 9.3.6  Battery Charging Management
        1. 9.3.6.1 Autonomous Charging Cycle
        2. 9.3.6.2 Battery Charging Profile
        3. 9.3.6.3 Charging Termination
        4. 9.3.6.4 Thermistor Qualification
          1. 9.3.6.4.1 JEITA Guideline Compliance During Charging Mode
          2. 9.3.6.4.2 Boost Mode Thermistor Monitor During Battery Discharge Mode
        5. 9.3.6.5 Charging Safety Timer
      7. 9.3.7  Ship Mode and QON Pin
        1. 9.3.7.1 BATFET Disable (Enter Ship Mode)
        2. 9.3.7.2 BATFET Enable (Exit Ship Mode)
        3. 9.3.7.3 BATFET Full System Reset
      8. 9.3.8  Status Outputs ( STAT, INT )
        1. 9.3.8.1 Charging Status Indicator (STAT)
        2. 9.3.8.2 Interrupt to Host ( INT)
      9. 9.3.9  Protections
        1. 9.3.9.1 Voltage and Current Monitoring in Buck Mode
          1. 9.3.9.1.1 Input Over-Voltage Protection (ACOV)
          2. 9.3.9.1.2 System Over-Voltage Protection (SYSOVP)
        2. 9.3.9.2 Voltage and Current Monitoring in Boost Mode
          1. 9.3.9.2.1 Boost Mode Over-Voltage Protection
        3. 9.3.9.3 Thermal Regulation and Thermal Shutdown
          1. 9.3.9.3.1 Thermal Protection in Buck Mode
          2. 9.3.9.3.2 Thermal Protection in Boost Mode
        4. 9.3.9.4 Battery Protection
          1. 9.3.9.4.1 Battery Over-Voltage Protection (BATOVP)
          2. 9.3.9.4.2 Battery Over-Discharge Protection
          3. 9.3.9.4.3 System Over-Current Protection
      10. 9.3.10 Serial Interface
        1. 9.3.10.1 Data Validity
        2. 9.3.10.2 START and STOP Conditions
        3. 9.3.10.3 Byte Format
        4. 9.3.10.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.3.10.5 Slave Address and Data Direction Bit
        6. 9.3.10.6 Single Read and Write
        7. 9.3.10.7 Multi-Read and Multi-Write
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
    5. 9.5 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor and Resistor
        3. 10.2.2.3 Output Capacitor
    3. 10.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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8.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV and VVBUS > VBAT + VSLEEP, TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IQ_BAT  Quiescent battery current (BATSNS, BAT, SYS, SW) VBAT = 4.5 V, VBUS floating or VBUS = 0V - 5 V, SCL, SDA = 0 V or 1.8 V, TJ < 85 °C, BATFET enabled  9.5 15 µA
ISHIP_BAT  Shipmode battery current (BATSNS, BAT, SYS, SW) VBAT = 4.5 V, VBUS floating or VBUS = 0V - 5 V, SCL, SDA = 0 V or 1.8 V, TJ < 85 °C, BATFET disabled 7 9.5 µA
IVBUS Input current (VBUS) in buck mode when converter is switching VBUS=5 V, charge disabled, converter switching, ISYS = 0 A 2.3 mA
IHIZ_VBUS  Quiescent input current in HIZ VAC/VBUS = 5 V, HIZ mode, no battery 37 50 µA
VAC/VBUS = 12 V, HIZ mode, no battery 68 90 µA
IBST Quiescent battery current (BATSNS, BAT, SYS, SW) in boost mode when converter is switching VBAT = 4.5 V, VBUS = 5 V, boost mode enabled, converter switching, IPMID = 0A 2.4 mA
VBUS / VBAT SUPPLY
VVBUS_OP VBUS operating range 4 13.5 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.3 3.7 V
VVBUS_UVLO VBUS falling to turnoff I2C, no battery VBUS falling 3 3.3 V
VVBUS_PRESENT VBUS to enable REGN VBUS rising 3.65 3.9 V
VVBUS_PRESENTZ VBUS to disable REGN VBUS falling 3.15 3.4 V
VSLEEP Enter Sleep mode threshold VBUS falling, VBUS - VBAT, VBAT = 4V 15 60 110 mV
VSLEEPZ Exit Sleep mode threshold VBUS rising, VBUS - VBAT, VBAT = 4V 115 220 340 mV
VACOV  VAC overvoltage rising threshold to turn of switching VAC rising, OVP[1:0]=00 5.45 5.85 6.07 V
VAC rising, OVP[1:0]=01 6.1 6.4 6.75 V
VAC rising, OVP[1:0]=10 10.45 11 11.55 V
VAC rising, OVP[1:0]=11 (default) 13.5 14.2 14.85 V
VAC overvoltage falling threshold to resume switching VAC falling, OVP[1:0]=00 5.2 5.6 5.8 V
VAC falling, OVP[1:0]=01 5.8 6.2 6.45 V
VAC falling, OVP[1:0]=10 10 10.7 11.1 V
VAC falling, OVP[1:0]=11 (default) 13 13.9 14.5 V
VBAT_UVLOZ BAT voltage for active I2C, no VBUS VBAT rising 2.5 V
VBAT_DPLZ BAT depletion rising threshold to turn on BATFET VBAT rising 2.35 2.8 V
VBAT_DPL BAT depletion falling threshold to turn off BATFET VBAT falling 2.18 2.40 2.55 V
VBAT_DPL BAT depletion falling threshold to turn off BATFET VBAT falling TJ = 25°C 2.40 2.50 V
VPOORSRC Bad adapter detection threshold VBUS falling 3.75 3.9 4.0 V
POWER-PATH MANAGEMENT
VSYS_MIN Typical minimum system regulation voltage VBAT=3.2 V < SYS_MIN = 3.5 V, ISYS = 0 A 3.5 3.65 V
VSYS_OVP System overvoltage threshold VREG = 4.35 V, Charge disabled, ISYS = 0 A 4.7 V
RON_RBFET Blocking FET on-resistance 45 mΩ
RON_HSFET High-side switching FET on-resistance 62 mΩ
RON_LSFET Low-side switching FET on-resistance 71 mΩ
VBATFET_FWD BATFET forward voltage in supplement mode BAT discharge current 10 mA, converter running 30 mV
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 3.49 4.51 V
VREG_STEP Typical charge voltage step 4.29 V < VREG < 4.51 V 10 mV
VREG_ACC Charge voltage accuracy VREG = 4.09 V, TJ = –40°C - 85°C 4.073 4.09 4.106 V
VREG_ACC Charge voltage accuracy VREG = 4.19 V, TJ = –40°C - 85°C 4.173 4.19 4.200 V
VREG_ACC Charge voltage accuracy VREG = 4.35 V, TJ = –40°C - 85°C 4.332 4.35 4.367 V
VREG_ACC Charge voltage accuracy VREG = 4.45 V, TJ = –40°C - 85°C 4.432 4.45 4.468 V
ICHG_RANGE  Typical charge current regulation range 0 3 A
ICHG_STEP Typical charge current regulation step 60 mA
ICHG_ACC  Fast charge current regulation accuracy ICHG = 0.24 A, VBAT = 3.1 V or 3.8 V, TJ = –40°C - 85°C 0.2112 0.24 0.2688 A
ICHG = 0.72 A, VBAT = 3.1 V or 3.8 V, TJ = –40°C - 85°C 0.6768 0.72 0.7632 A
ICHG = 1.38 A, VBAT = 3.1 V or 3.8 V, TJ = –40°C - 85°C 1.2972 1.38 1.4628 A
IPRECHG_RANGE Typical pre-charge current range 60 780 mA
IPRECHG_STEP Typical pre-charge current step 60 mA
IPRECHG_ACC  Precharge current accuracy VBAT = 2.6 V, IPRECHG = 120 mA 102 120 138 mA
VBAT = 2.6 V, IPRECHG = 240 mA 204 240 276 mA
ITERM_RANGE Typical termination current range 60 780 mA
ITERM_STEP  Typical termination current step 60 mA
ITERM_ACC  Termination current accuracy ITERM = 180 mA, ICHG > 780 mA, VREG = 4.35 V, TJ = –40°C - 85°C 162 180 192 mA
ITERM = 60mA, ICHG = < 780 mA, VREG = 4.35 V, TJ = –40°C - 85°C 42 60 78 mA
VBAT_SHORTZ Battery short voltage rising threshold to start pre-charge VBAT rising 2.13 2.25 2.35 V
VBAT_SHORT Battery short voltage falling threshold to stop pre-charge VBAT falling 1.85 2 2.15 V
IBAT_SHORT Battery short trickle charging current VBAT < VBAT_SHORTZ 70 90 110 mA
VBATLOWV Battery LOWV rising threshold to start fast-charge VBAT rising 3 3.12 3.24 V
Battery LOWV falling threshold to stop fast-charge VBAT falling 2.7 2.8 2.9 V
VRECHG  Battery recharge threshold VRECHG=0, VBAT falling (default) 90 120 150 mV
VRECHG=1, VBAT falling 185 210 245 mV
ISYS_LOAD System discharge load current during SYSOVP 30 mA
RON_BATFET Battery FET on-resistance TJ = –40°C - 85°C 19.5 26 mΩ
TJ = –40°C - 125°C 19.5 30 mΩ
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP Battery overvoltage rising threshold VBAT rising, as percentage of VREG 103 104 105 %
Battery overvoltage falling threshold VBAT falling, as percentage of VREG 101 102 103 %
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Typical input voltage regulation range 3.9 5.4 V
VINDPM_STEP Typical input voltage regulation step 100 mV
VINDPM_ACC  Typical input voltage regulation accuracy 4.365 4.5 4.635 V
VINDPM_TRACK  VINDPM threshold to track battery voltage VBAT = 4.35 V, VINDPM_BAT_TRACK = VBAT + 200 mV 4.45 4.55 4.74 V
IINDPM_RANGE Typical input current regulation range 0.1 3.2 A
IINDPM_STEP Typical input current regulation step 100 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 500 mA (TJ=-40°C - 85°C) 450 465 500 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 900 mA (TJ=-40°C-85°C) 750 835 900 mA
IINDPM_ACC Input current regulation accuracy IINDPM = 1500 mA (TJ=-40°C-85°C) 1300 1390 1500 mA
D+ / D- Detection
VDP_SRC D+ line source voltage  500 600 700 mV
IDP_SRC D+ line data contact detect current source VD + = 200 mV, 7 10 14 µA
IDP_SINK D+ line sink current VD + = 500 mV, 50 100 150 µA
VDP_DAT_REF D+ line data detect voltage D+ pin Rising,  250 400 mV
VDP_LGC_LOW D+ line logic low.  D+ pin Rising, 800 mV
RDP_DWN D+ line pull-down resistance VD+ = 500 mV 14.25 24.8 kΩ
ID+_LKG Leakage current into D+ line Pull up to 1.8 V –1 1 µA
VDM_SRC D- line source voltage  500 600 700 mV
IDM_SINK D- line sink current VD- = 500 mV, 50 100 150 µA
VDM_DAT_REF D- line data detect voltage D- pin Rising, 250 400 mV
RDM_DWN D- line pull-down resistance VD- = 500 mV 14.25 24.8 kΩ
ID-_LKG Leakage current into D- line Pull up to 1.8 V –1 1 µA
VD+/D- _2p8 D+/D- comparator threshold for non-standard adapter 2.55 2.85 V
VD+/D- _2p0 D+/D- comparator threshold for non-standard adapter 1.85 2.15 V
VD+/D- _1p2 D+/D- comparator threshold for non-standard adapter 1.05 1.35 V
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 90°C 90 °C
TREG = 110°C 110 °C
TSHUT Thermal Shutdown Rising threshold Temperature Increasing 150 °C
Thermal Shutdown Falling threshold Temperature Decreasing 130 °C
CHARGE MODE THERMISTOR COMPARATOR (JEITA 616J or HOT/COLD 616)
VT1_RISE% TS pin voltage rising threshold, Charge suspended above this voltage. As Percentage to REGN (0°C w/ 103AT) 72.4 73.3 74.2 %
VT1_FALL% TS pin voltage falling threshold. Charge re-enabled to 20% of ICHG and VREG below this
voltage. 		 As Percentage to REGN 71.5 72 72.5 %
VT2_RISE%  TS pin voltage rising threshold, Charge back to 20% of ICHG and VREG above this voltage.  As Percentage to REGN, JEITA_T2 = 5°C w/ 103AT 70.25 70.75 71.25 %
As Percentage to REGN, JEITA_T2 = 10°C w/ 103AT 67.75 68.25 68.75 %
As Percentage to REGN, JEITA_T2 = 15°C w/ 103AT 64.75 65.25 65.75 %
As Percentage to REGN, JEITA_T2 = 20°C w/ 103AT 61.75 62.25 62.75 %
VT2_FALL% TS pin voltage falling threshold. Charge back to ICHG and VREG below this voltage.  As Percentage to REGN, JEITA_T2=5°C w/ 103AT 68.7 69.2 69.7 %
As Percentage to REGN, JEITA_T2=10°C  w/ 103AT 66.45 66.95 67.45 %
As Percentage to REGN, JEITA_T2=15°C  w/ 103AT 63.7 64.2 64.7 %
As Percentage to REGN, JEITA_T2=20°C  w/ 103AT 60.7 61.2 61.7 %
VT3_FALL% TS pin voltage falling threshold. Charge to ICHG and 4.1V below this voltage.  As Percentage to REGN, JEITA_T3=40°C  w/ 103AT 47.75 48.25 48.75 %
As Percentage to REGN, JEITA_T3=45°C  w/ 103AT 44.25 44.75 45.25 %
As Percentage to REGN, JEITA_T3=50°C  w/ 103AT 40.2 40.7 41.2 %
As Percentage to REGN, JEITA_T3=55°C  w/ 103AT 37.2 37.7 38.2 %
VT3_RISE% TS pin voltage rising threshold. Charge back to ICHG and VREG above this voltage.  As Percentage to REGN, JEITA_T3 = 40°C w/ 103AT 48.8 49.3 49.8 %
As Percentage to REGN, JEITA_T3 = 45°C w/ 103AT 45.3 45.8 46.3 %
As Percentage to REGN, JEITA_T3 = 50°C w/ 103AT 41.3 41.8 42.3 %
As Percentage to REGN, JEITA_T3 = 55°C w/ 103AT 38.5 39 39.5 %
VT5_FALL% TS pin voltage falling threshold, charge suspended below this voltage.  As Percentage to REGN (60°C w/ 103AT) 33.7 34.2 35.1 %
VT5_RISE% TS pin voltage rising threshold. Charge back to ICHG and 4.1V above this voltage.  As Percentage to REGN 35 35.5 36 %
BOOST MODE THERMISTOR COMPARATOR (HOT/COLD)
VBCOLD_RISE% TS pin voltage rising threshold, boost mode is suspended above this voltage.  As Percentage to REGN (–19.5°C w/ 103AT) 79.5 80 80.5 %
VBCOLD_FALL% TS pin voltage falling threshold As Percentage to REGN (0°C w/ 103AT) 72 %
VBHOT_FALL% TS pin voltage threshold. boost mode is suspended below this voltage.  As Percentage to REGN, (64°C w/ 103AT) 30.2 31.2 32.2 %
VBHOT_RISE% TS pin voltage rising threshold As Percentage to REGN, (55°C w/ 103AT), REG0C[1:0] = 11 39 %
SWITCHING CONVERTER
FSW PWM switching frequency Oscillator frequency 1.32 1.5 1.68 MHz
DMAX Maximum PWM Duty Cycle 97 %
BOOST MODE CONVERTER
VBST_BAT Battery voltage exiting boost mode BAT falling 2.4 2.5 2.6 V
VBST_RANGE Typical boost mode voltage regulation range 4.6 5.15 V
VBST_ACC Boost mode voltage regulation accuracy IVBUS = 0 A, BOOST_V = 5 V 4.85 5 5.15 V
IBST_RANGE Typical boost mode current regulation  0.5 1.2 A
IBST_ACC  Boost mode maximum output current limit 1.2 1.4 1.6 A
IBST_OCP_Q1  Boost mode battery discharge current clamp on RBFET Q1 BOOST_LIM = 0.5 A 0.5 0.72 A
ISYS_OCP_Q4 Boost mode battery discharge current clamp on BATFET Q4 9 10 A
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5 V, IREGN = 20 mA 4.58 4.7 4.8 V
VVBUS = 9 V, IREGN = 20 mA 5.6 6 6.5 V
IREGN REGN LDO current limit VVBUS = 5 V, VREGN = 3.8 V 50 mA
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL Pull up rail 1.8 V 1.3 V
VIL Input low threshold level Pull up rail 1.8 V 0.4 V
VOL Output low threshold level Sink current = 5 mA 0.4 V
IBIAS High-level leakage current Pull up rail 1.8 V 1 µA
VIH_SDA Input high threshold level, SDA Pull up rail 1.8 V 1.3 V
VIL_SDA Input low threshold level Pull up rail 1.8 V 0.4 V
VOL_SDA Output low threshold level Sink current = 5 mA 0.4 V
IBIAS_SDA High-level leakage current Pull up rail 1.8 V 1 µA
VIH_SCL Input high threshold level, SDA Pull up rail 1.8 V 1.3 V
VIL_SCL Input low threshold level Pull up rail 1.8 V 0.4 V
VOL_SCL Output low threshold level Sink current = 5 mA 0.4 V
IBIAS_SCL High-level leakage current Pull up rail 1.8 V 1 µA
LOGIC INPUT PIN
VIH Input high threshold level (/CE) 1.3 V
VIL  Input low threshold level (/CE) 0.4 V
IIN_BIAS  High-level leakage current (/CE) Pull up rail 1.8 V 1 µA
LOGIC OUTPUT PIN
VOL Output low threshold level (/INT, STAT, /PG) Sink current = 5 mA 0.4 V
IOUT_BIAS High-level leakage current (/INT, STAT, /PG) Pull up rail 1.8 V 1 µA
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
IHSFET_OCP HSFET cycle-by-cycle over-current threshold 5.2 8.0 A