ZHCSRC2A December   2022  – March 2024 AWRL6432

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1.      11
      2.      12
      3.      13
      4.      14
      5.      15
      6.      16
      7.      17
      8.      18
      9.      19
      10.      20
      11.      21
      12.      22
      13.      23
      14.      24
      15.      25
      16.      26
      17.      27
    3.     28
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 Power Optimized 3.3V I/O Topology
      2. 7.6.2 BOM Optimized 3.3V I/O Topology
      3. 7.6.3 Power Optimized 1.8V I/O Topology
      4. 7.6.4 BOM Optimized 1.8V I/O Topology
      5. 7.6.5 System Topologies
        1. 7.6.5.1 Power Topologies
          1. 7.6.5.1.1 BOM Optimized Mode
          2. 7.6.5.1.2 Power Optimized Mode
      6. 7.6.6 Internal LDO output decoupling capacitor and layout conditions for BOM optimized topology
        1. 7.6.6.1 Single-capacitor rail
          1. 7.6.6.1.1 1.2V Digital LDO
        2. 7.6.6.2 Two-capacitor rail
          1. 7.6.6.2.1 1.2V RF LDO
          2. 7.6.6.2.2 1.2V SRAM LDO
          3. 7.6.6.2.3 1.0V RF LDO
      7. 7.6.7 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  RF Specification
    10. 7.10 Supported DFE Features
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Timing and Switching Characteristics
      1. 7.13.1  Power Supply Sequencing and Reset Timing
      2. 7.13.2  Synchronized Frame Triggering
      3. 7.13.3  Input Clocks and Oscillators
        1. 7.13.3.1 Clock Specifications
      4. 7.13.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.13.4.1 McSPI Features
        2. 7.13.4.2 SPI Timing Conditions
        3. 7.13.4.3 SPI—Controller Mode
          1. 7.13.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.13.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.13.4.4 SPI—Peripheral Mode
          1. 7.13.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.13.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.13.5  RDIF Interface Configuration
        1. 7.13.5.1 RDIF Interface Timings
        2. 7.13.5.2 RDIF Data Format
      6. 7.13.6  LIN
      7. 7.13.7  General-Purpose Input/Output
        1. 7.13.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.13.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.13.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 7.13.9  Serial Communication Interface (SCI)
        1. 7.13.9.1 SCI Timing Requirements
      10. 7.13.10 Inter-Integrated Circuit Interface (I2C)
        1. 7.13.10.1 I2C Timing Requirements
      11. 7.13.11 Quad Serial Peripheral Interface (QSPI)
        1. 7.13.11.1 QSPI Timing Conditions
        2. 7.13.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.13.11.3 QSPI Switching Characteristics
      12. 7.13.12 JTAG Interface
        1. 7.13.12.1 JTAG Timing Conditions
        2. 7.13.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.13.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 功能方框图
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Automotive Interface
      7. 8.3.7 Host Interface
      8. 8.3.8 Application Subsystem Cortex-M4F
      9. 8.3.9 Hardware Accelerator (HWA1.2) Features
        1. 8.3.9.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 8.4 Other Subsystems
      1. 8.4.1 GPADC Channels (Service) for User Application
      2. 8.4.2 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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5 Device Comparison

The following table compares the features of radar devices.

Table 5-1 Device Features Comparison
FUNCTION

AWRL6432

AWRL1432

 AWR6843AOP(1) AWR6843(1) AWR1843(1) AWR1843AOP(1) AWR1642 AWR1443
Antenna on Package (AOP) - - Yes - - Yes - -
Number of receivers 3 3 4 4 4 4 4 4
Number of transmitters 2 2 3(2) 3(2) 3(2) 3(2) 2 3
RF frequency range 57 to 64GHz 76 to 81GHz 60 to 64 GHz 60 to 64 GHz 76 to 81 GHz 60 to 64GHz 76 to 81 GHz 76 to 81 GHz
On-chip memory 1MB 1MB 1.75MB 1.75MB 2MB 1.75MB 1.5MB 576KB
Max I/F (Intermediate Frequency) (MHz) 5 5 10 10 10 10 5 5
Max real sampling rate (Msps) 12.5 12.5 25 25 25 25 12.5 12.5
Max complex sampling rate (Msps) - - 12.5 12.5 12.5 12.5 6.25 6.25
Safety and Security
Functional Safety -Compliance ASIL-B Targeted ASIL-B Targeted(3) ASIL-B ASIL-B ASIL-B ASIL-B - -
Device Security(4) - - Yes Yes Yes Yes Yes -
Processors
MCU M4F M4F R4F R4F R4F R4F R4F R4F
DSP - - C674x C674x C674x C674x C674x -
HWA Yes Yes Yes Yes Yes Yes - Yes
Peripherals
Serial Peripheral Interface (SPI) ports 2 2 2 2 2 2 2 1
Quad Serial Peripheral Interface (QSPI) Yes Yes Yes Yes Yes Yes Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1 1 1 1 1 1 1
Controller Area Network (Classical CAN) interface - - - - 1 - 1 1
Controller Area Network (CAN-FD) interface 1 1 2 2 1 2 - -
DSP Trace - - Yes Yes Yes Yes Yes -
PWM Yes Yes Yes Yes Yes Yes Yes -

DMM Interface

 - - Yes Yes Yes Yes Yes -
Hardware In Loop (HIL/DMM) - - Yes Yes Yes Yes Yes -
GPADC Yes Yes Yes Yes Yes Yes Yes Yes
ADC Raw Data Capture RDIF RDIF LVDS LVDS LVDS LVDS LVDS LVDS
LIN Yes Yes - - - - - -
UART 2 2 2 2 2 2 2 2
1V bypass mode N/A N/A Yes Yes Yes Yes Yes Yes
JTAG Yes Yes Yes Yes Yes Yes Yes Yes
Per Chirp configurable TX phase shifter BPM Only BPM Only Yes(5) Yes(5) Yes(5) Yes(5) BPM only BPM Only
Product status Product Preview (PP), Advance Information (AI), or Production Data (PD) PD(6) AI PD(6) PD(6) PD(6) PD(6) PD(6) PD(6)
(1) Developed for Functional Safety applications, the device supports hardware integrity up to ASIL-B. Refer to the related documentation for more details. Non-Functional Safety Variants are also available for AWRL6432 device.
(2) 3 Tx Simultaneous operation is supported only with 1V LDO bypass and PA LDO disable mode. In this mode, the 1V supply needs to be fed on the VOUT PA pin.
(3) As the certification can get secured at different times and post certificate the target will be updated to “compliant” from “compliance targeted” only in related data sheets, please refer to the respective data sheets for most recent compliance status.
(4) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part variants as indicated by the Device Type identifier in Section 3, Device Information table.
(5) 6 bits linear Phase Shifter.
(6) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty.