At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
| SFDR = 89.7dBc |
SINAD = 73dBFS |
SNR = 73.1dBFS |
| THD = 88.4dBc |
|
|
Figure 6-6 FFT
For 20MHz Input Signal
| SFDR = 73.4dBc |
SINAD = 67.7dBFS |
SNR = 69.2dBFS |
| THD = 72.3dBc |
|
|
Figure 6-8 FFT
For 300MHz Input Signal
| Each Tone at −7dBFS Amplitude |
fIN1
= 46MHz |
| Two−Tone
IMD=96.9dBFS |
SFDR=105.3dBFS |
fIN2
= 50MHz |
Figure 6-10 FFT
For Two-Tone Input Signal
Figure 6-12 SNR
vs Input Frequency
Figure 6-14 SFDR
vs Gain And Input Frequency
Figure 6-16 Performance vs Input Amplitude
Figure 6-18 Performance vs Input Common-Mode Voltage
Figure 6-20 SFDR
vs Temperature And AVDD Supply
Figure 6-22 Performance vs DRVDD Supply Voltage
Figure 6-24 Performance vs Input Clock Amplitude
Figure 6-26 Integrated Nonlinearity
| SFDR = 86.7dBc |
SINAD = 71.2dBFS |
SNR = 71.4dBFS |
| THD = 83.8dBc |
|
|
Figure 6-7 FFT
For 170MHz Input Signal
| Each Tone at −7dBFS Amplitude |
fIN1
= 185MHz |
| Two−Tone IMD =
94dBFS |
SFDR =
92.8dBFS |
fIN2
= 190MHz |
Figure 6-9 FFT
For Two-Tone Input Signal
Figure 6-11 SFDR
vs Input Frequency
Figure 6-13 SNR
vs Input Frequency (CMOS)
Figure 6-15 SINAD
vs Gain And Input Frequency
Figure 6-17 Performance vs Input Amplitude
Figure 6-19 Performance vs Input Common-Mode Voltage
Figure 6-21 SNR
vs Temperature And AVDD Supply
Figure 6-23 Performance vs Input Clock Amplitude
Figure 6-25 Performance vs Input Clock Duty Cycle
Figure 6-27 Output Noise Histogram (With Inputs Shorted To VCM)