ZHCSCA6B April   2014  – October 2020 ADS4245-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics: LVDS And CMOS Modes
    9. 6.9  Typical Characteristics:
    10. 6.10 Typical Characteristics: General
    11. 6.11 Typical Characteristics: Contour
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
      2. 7.4.2 Gain For SFDR/SNR Trade-Off
      3. 7.4.3 Offset Correction
      4. 7.4.4 Power-Down
        1. 7.4.4.1 Global Power-Down
        2. 7.4.4.2 Channel Standby
        3. 7.4.4.3 Input Clock Stop
      5. 7.4.5 Digital Output Information
        1. 7.4.5.1 Output Interface
        2. 7.4.5.2 DDR LVDS Outputs
        3. 7.4.5.3 LVDS Buffer
        4. 7.4.5.4 Parallel CMOS Interface
        5. 7.4.5.5 CMOS Interface Power Dissipation
        6. 7.4.5.6 Multiplexed Mode Of Operation
        7. 7.4.5.7 Output Data Format
      6. 7.4.6 Device Configuration
        1. 7.4.6.1 Parallel Configuration Only
        2. 7.4.6.2 Serial Interface Configuration Only
        3. 7.4.6.3 Using Both Serial Interface And Parallel Controls
        4. 7.4.6.4 Parallel Configuration Details
        5. 7.4.6.5 Serial Interface Details
          1. 7.4.6.5.1 Register Initialization
          2. 7.4.6.5.2 Serial Register Readout
    5. 7.5 Serial Register Map
    6. 7.6 Description Of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Clock Input
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Input
        1. 8.2.1.1 Design Requirements for Drive Circuits
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding
      2. 10.1.2 Supply Decoupling
      3. 10.1.3 Exposed Pad
      4. 10.1.4 Routing Analog Inputs
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Support
        1. 11.1.1.1 Definition Of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

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5 Pin Configuration and Functions

GUID-B0C0A650-BCCC-4D77-BE46-AF3FA9FF47C4-low.svg
The PowerPAD™ is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 5-1 RGC Package (LVDS Mode) (1),VQFN-64,(Top View)
Table 5-1 Pin Functions: LVDS Mode
NO. NAME # OF PINS FUNCTION DESCRIPTION
1, 48 DRVDD 2 Input Output buffer supply
12 RESET 1 Input Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this terminal or by using the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET terminal must be permanently tied high. SCLK and SEN are used as parallel control terminals in this mode. This terminal has an internal 150kΩ pull-down resistor.
13 SCLK 1 Input This terminal functions as a serial interface clock input when RESET is low. It controls the low-speed mode selection when RESET is tied high; see Table 7-6 for detailed information. This terminal has an internal 150kΩ pull-down resistor.
14 SDATA 1 Input Serial interface data input; this terminal has an internal 150kΩ pull-down resistor.
15 SEN 1 Input This terminal functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; see Table 7-7 for detailed information. This terminal has an internal 150kΩ pull-up resistor to AVDD.
16, 22, 33, 34 AVDD 4 Input Analog power supply
17, 18, 21, 24, 27, 28, 31, 32 AGND 8 Input Analog ground
19 INP_B 1 Input Differential analog positive input, channel B
20 INM_B 1 Input Differential analog negative input, channel B
23 VCM 1 Output This terminal outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input terminals
25 CLKP 1 Input Differential clock positive input
26 CLKM 1 Input Differential clock negative input
29 INP_A 1 Input Differential analog positive input, channel A
30 INM_A 1 Input Differential analog negative input, channel A
35 CTRL1 1 Input Digital control input terminals. Together, they control the various power-down modes.
36 CTRL2 1 Input Digital control input terminals. Together, they control the various power-down modes.
37 CTRL3 1 Input Digital control input terminals. Together, they control the various power-down modes.
49 DRGND 2 Input Output buffer ground
56 CLKOUTM 1 Output Differential output clock, complement
57 CLKOUTP 1 Output Differential output clock, true
64 SDOUT 1 Output This terminal functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this terminal is in high-impedance state.
40 DA0M 2 Output Channel A differential output data pair, D0 and D1 multiplexed
41 DA0P
42 DA2M 2 Output Channel A differential output data D2 and D3 multiplexed
43 DA2P
44 DA4M 2 Output Channel A differential output data D4 and D5 multiplexed
45 DA4P
46 DA6M 2 Output Channel A differential output data D6 and D7 multiplexed
47 DA6P
50 DA8M 2 Output Channel A differential output data D8 and D9 multiplexed
51 DA8P
52 DA10M 2 Output Channel A differential output data D10 and D11 multiplexed
53 DA10P
54 DA12M 2 Output Channel A differential output data D12 and D13 multiplexed
55 DA12P
60 DB0M 2 Output Channel B differential output data pair, D0 and D1 multiplexed
61 DB0P
62 DB2M 2 Output Channel B differential output data D2 and D3 multiplexed
63 DB2P
2 DB4M 2 Output Channel B differential output data D4 and D5 multiplexed
3 DB4P
4 DB6M 2 Output Channel B differential output data D6 and D7 multiplexed
5 DB6P
6 DB8M 2 Output Channel B differential output data D8 and D9 multiplexed
7 DB8P
8 DB10M 2 Output Channel B differential output data D10 and D11 multiplexed
9 DB10P
10 DB12M 2 Output Channel B differential output data D12 and D13 multiplexed
11 DB12P
38, 39, 58, 59 NC 4 — Do not connect, must be floated
GUID-34F637E2-7183-4959-B6BC-66E86DD6344A-low.svg
The PowerPAD™ is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 5-2 RGC Package (CMOS Mode), (1)VQFN-64,(Top View)
Table 5-2 Pin Functions: CMOS Mode
NO. NAME # OF PINS FUNCTION DESCRIPTION
1, 48 DRVDD 2 Input Output buffer supply
12 RESET 1 Input Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this terminal or by using the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET terminal must be permanently tied high. SDATA and SEN are used as parallel control terminals in this mode. This terminal has an internal 150kΩ pull-down resistor.
13 SCLK 1 Input This terminal functions as a serial interface clock input when RESET is low. It controls the low-speed mode when RESET is tied high; see Table 7-6 for detailed information. This terminal has an internal 150kΩ pull-down resistor.
14 SDATA 1 Input Serial interface data input; this terminal has an internal 150kΩ pull-down resistor.
15 SEN 1 Input This terminal functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; see Table 7-7 for detailed information. This terminal has an internal 150kΩ pull-up resistor to AVDD.
16, 22, 33, 34 AVDD 4 Input Analog power supply
17, 18, 21, 24, 27, 28, 31, 32 AGND 8 Input Analog ground
19 INP_B 1 Input Differential analog positive input, channel B
20 INM_B 1 Input Differential analog negative input, channel B
23 VCM 1 Output This terminal outputs the common-mode voltage (0.95V) that can be used externally to bias the analog input terminals
25 CLKP 1 Input Differential clock positive input
26 CLKM 1 Input Differential clock negative input
29 INP_A 1 Input Differential analog positive input, channel A
30 INM_A 1 Input Differential analog negative input, channel A
35 CTRL1 1 Input Digital control input terminals. Together, they control various power-down modes.
36 CTRL2 1 Input Digital control input terminals. Together, they control various power-down modes.
37 CTRL3 1 Input Digital control input terminals. Together, they control various power-down modes.
49 DRGND 2 Input Output buffer ground
56 UNUSED 1 — This terminal is not used in the CMOS interface
57 CLKOUT 1 Output CMOS output clock
64 SDOUT 1 Output This terminal functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this terminal is in high-impedance state.
40 DA0 12 Output Channel A ADC output data bits, CMOS levels
41 DA1
42 DA2
43 DA3
44 DA4
45 DA5
46 DA6
47 DA7
50 DA8
51 DA9
52 DA10
53 DA11
54 DA12 2 Output Channel A ADC output data bits, CMOS levels
55 DA13
60 DB0 12 Output Channel B ADC output data bits, CMOS levels
61 DB1
62 DB2
63 DB3
2 DB4
3 DB5
4 DB6
5 DB7
6 DB8
7 DB8
8 DB10
9 DB11
10 DB12 2 Output Channel B ADC output data bits, CMOS levels
11 DB13
38, 39, 58, 59 NC 1 — Do not connect, must be floated