ZHCSCA6B April   2014  – October 2020 ADS4245-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics: LVDS And CMOS Modes
    9. 6.9  Typical Characteristics:
    10. 6.10 Typical Characteristics: General
    11. 6.11 Typical Characteristics: Contour
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
      2. 7.4.2 Gain For SFDR/SNR Trade-Off
      3. 7.4.3 Offset Correction
      4. 7.4.4 Power-Down
        1. 7.4.4.1 Global Power-Down
        2. 7.4.4.2 Channel Standby
        3. 7.4.4.3 Input Clock Stop
      5. 7.4.5 Digital Output Information
        1. 7.4.5.1 Output Interface
        2. 7.4.5.2 DDR LVDS Outputs
        3. 7.4.5.3 LVDS Buffer
        4. 7.4.5.4 Parallel CMOS Interface
        5. 7.4.5.5 CMOS Interface Power Dissipation
        6. 7.4.5.6 Multiplexed Mode Of Operation
        7. 7.4.5.7 Output Data Format
      6. 7.4.6 Device Configuration
        1. 7.4.6.1 Parallel Configuration Only
        2. 7.4.6.2 Serial Interface Configuration Only
        3. 7.4.6.3 Using Both Serial Interface And Parallel Controls
        4. 7.4.6.4 Parallel Configuration Details
        5. 7.4.6.5 Serial Interface Details
          1. 7.4.6.5.1 Register Initialization
          2. 7.4.6.5.2 Serial Register Readout
    5. 7.5 Serial Register Map
    6. 7.6 Description Of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Clock Input
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Input
        1. 8.2.1.1 Design Requirements for Drive Circuits
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding
      2. 10.1.2 Supply Decoupling
      3. 10.1.3 Exposed Pad
      4. 10.1.4 Routing Analog Inputs
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Support
        1. 11.1.1.1 Definition Of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

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8.2.1.2 Detailed Design Procedure

Two example driving circuit configurations are shown in Figure 8-7 and Figure 8-8—one optimized for low bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. Note that both of the drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished by a 25Ω resistor from each input to the 1.5V common-mode (VCM) from the device. This architecture allows the analog inputs to be biased around the required common-mode voltage.

The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch; good performance is obtained for high-frequency input signals. An additional termination resistor pair may be required between the two transformers, as shown in Figure 8-7, Figure 8-8, and Figure 8-9. The center point of this termination is connected to ground to improve the balance between the P and M sides. The values of the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (in the case of 50Ω source impedance).

GUID-4DF584F7-77BB-47CD-917F-4C9F4B8133B1-low.gifFigure 8-7 Drive Circuit With Low Bandwidth (For Low Input Frequencies Less Than 150MHz)
GUID-5373A43E-7CD4-4669-8142-E6CD30FD0EDD-low.gifFigure 8-8 Drive Circuit With High Bandwidth (For High Input Frequencies Greater Than 150MHz And Less Than 270MHz)
GUID-5CC55319-FCBA-45DE-81D1-08D07DF93BE2-low.gifFigure 8-9 Drive Circuit With Very High Bandwidth (Greater Than 270MHz)

All of these examples show 1:1 transformers being used with a 50Ω source. As explained in the Drive Circuit Requirements section, this configuration helps to present a low source impedance to absorb the sampling glitches. With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).

In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance, as shown in Figure 8-10. Such filters present low source impedance at the high frequencies corresponding to the sampling glitch and help avoid the performance loss with the high source impedance.

GUID-836CAB25-AEB3-4338-B5EB-C8806AFEA344-low.gifFigure 8-10 Drive Circuit With A 1:4 Transformer