ZHCSCA6B April 2014 – October 2020 ADS4245-EP
PRODUCTION DATA
The analog input consists of a switched-capacitor based, differential sample-and-hold (S/H) architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INP and INM terminals must be externally biased around a common-mode voltage of 0.95V, available on the VCM terminal. For a full-scale differential input, each input terminal (INP and INM) must swing symmetrically between VCM + 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The input sampling circuit has a high 3dB bandwidth that extends up to 550MHz (measured from the input terminals to the sampled voltage). Figure 8-6 shows an equivalent circuit for the analog input.