At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
![CMRR
vs Test Signal Frequency GUID-8033B6D3-3D41-46D3-A683-298AE897483E-low.gif](/ods/images/ZHCSCA6B/GUID-8033B6D3-3D41-46D3-A683-298AE897483E-low.gif)
Input Frequency = 40MHz |
50mVPP Signal
Superimposed |
on Input Common−Mode Voltage
0.95V |
Figure 6-28 CMRR
vs Test Signal Frequency![Analog Power vs Sampling Frequency GUID-4612CDFE-5397-496C-A6F9-1EE0FE6E24F4-low.gif](/ods/images/ZHCSCA6B/GUID-4612CDFE-5397-496C-A6F9-1EE0FE6E24F4-low.gif)
AVDD = 1.8V |
Input
Frequency = 2.5MHz |
|
|
|
Figure 6-30 Analog Power vs Sampling Frequency
Figure 6-32 Digital Power In Various Modes (LVDS)![PSRR
vs Test Signal Frequency GUID-CE7126AE-CE23-4412-9D7B-854167DE85F9-low.gif](/ods/images/ZHCSCA6B/GUID-CE7126AE-CE23-4412-9D7B-854167DE85F9-low.gif)
Input Frequency = 10MHz |
50mVPP Signal Superimposed on
AVDD Supply |
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|
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Figure 6-29 PSRR
vs Test Signal Frequency
Figure 6-31 Digital Power LVDS CMOS