ADC32RF4x 双通道 14 位 1.0–3.0GSPS 模数转换器 - ADC32RF45

ADC32RF45 (正在供货)

ADC32RF4x 双通道 14 位 1.0–3.0GSPS 模数转换器

 

描述

The ADC32RF45 device is a 14-bit, 3.0-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF45 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF45 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

特性

  • 14-Bit, Dual-Channel, 3.0-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 77-dBc Worst Spur
  • Spectral Performance (fIN = 1.78 GHz, –2 dBFS):
    • SNR: 58.8 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

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参数 与其它产品相比 高速 ADCs (>10MSPS)

 
Resolution (Bits)
Sample Rate (Max) (MSPS)
# Input Channels
SNR (dB)
ENOB (Bits)
SFDR (dB)
Power Consumption (Typ) (mW)
Input Range
Interface
Operating Temperature Range (C)
Analog Input BW (MHz)
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Rating
SINAD (dB)
Architecture
DNL (Max) (+/-LSB)
INL (Max) (+/-LSB)
Reference Mode
ADC32RF45 ADC12D1600 ADC12D1600RF ADC12D1800 ADC12D1800RF ADC12J1600 ADC12J2700 ADC12J4000
14    12    12    12    12    12    12    12   
3000    3200    3200    3600    3600    1600    2700    4000   
2    2    2    2    2    1    1    1   
62.7    58.5    59    58.6    58.6    55    55    55   
10.0    9.4    9.4    9.4    9.3         
69.0    70.3    67.9    73    68.1    70    71    71   
6400    3880    3880    4180    4400    1600    1800    2000   
1.35    0.8    0.8    0.8    0.8         
JESD204B    Parallel LVDS
Serial SPI Interface   
Parallel LVDS
Serial SPI Interface   
Parallel LVDS
Serial SPI Interface   
Parallel LVDS
Serial SPI Interface   
JESD204B    JESD204B    JESD204B   
-40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85    -40 to 85   
3200    2800    2700    2800    2700    3300    3300    3300   
Yes    Yes    Yes    Yes    Yes    No    No    No   
VQFN    BGA    BGA    BGA    BGA    VQFN    VQFN    VQFN   
72VQFN: 100 mm2: 10 x 10(VQFN)    292BGA: 729 mm2: 27 x 27(BGA)    292BGA: 729 mm2: 27 x 27(BGA)    292BGA: 729 mm2: 27 x 27(BGA)    292BGA: 729 mm2: 27 x 27(BGA)    68VQFN: 100 mm2: 10 x 10(VQFN)    68VQFN: 100 mm2: 10 x 10(VQFN)    68VQFN: 100 mm2: 10 x 10(VQFN)   
Catalog    Catalog    Catalog    Catalog    Catalog    Catalog    Catalog    Catalog   
61.8    58.2    58    58    57.7         
Pipeline    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating    Folding Interpolating   
  0.4    0.4    0.4    0.4         
  2.5    2.5    2.5    2.5         
Int    Int    Int    Int    Int    Int    Int    Int