ADC31RF80 14 位 3GSPS 射频采样宽带接收器和反馈集成电路 | 德州仪器 TI.com.cn

ADC31RF80
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14 位 3GSPS 射频采样宽带接收器和反馈集成电路

14 位 3GSPS 射频采样宽带接收器和反馈集成电路 - ADC31RF80
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描述

The ADC31RF80 device is a 14-bit, 3-GSPS, single-channel telecom receiver and feedback device that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC31RF80 delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

The ADC31RF80 comes with a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC31RF80 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



特性

  • 14-Bit, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up To 4.0 GHz
  • Aperture Jitter: 90 fS
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 61.4 dBFS
    • SFDR: 71-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.5 dBFS
    • SFDR: 65-dBc HD2, HD3
    • SFDR: 75-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 2 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Support at 12.5 Gbps
  • Total Power Dissipation: 3.2 W at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

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参数

与其它产品相比 高速 ADCs (>10MSPS) 邮件 下载到电子表格中
Part number 立即下单 Sample rate (Max) (MSPS) Features Resolution (Bits) Number of input channels SNR (dB) ENOB (Bits) SFDR (dB) Power consumption (Typ) (mW) Input range (Vp-p) Interface Operating temperature range (C) Analog input BW (MHz) Input buffer Package Group Package size: mm2:W x L (PKG) Rating Architecture
ADC31RF80 立即下单 3000     Decimating Filter
Ultra High Speed    
14     1     61.4     9.8     71     3200     1.35     JESD204B     -40 to 85     3200     Yes     VQFN | 72     72VQFN: 100 mm2: 10 x 10 (VQFN | 72)     Catalog     Pipeline    
ADC32RF80 无样片 3000     Decimating Filter
Ultra High Speed    
14     2     61.1     9.7     66     6400     1.35     JESD204B     -40 to 85     3200       VQFN | 72     72VQFN: 100 mm2: 10 x 10 (VQFN | 72)       Pipeline    
ADC32RF82 无样片 2456     Decimating Filter
Ultra High Speed    
14     2     61.2     9.7     67     5500     1.35     JESD204B     -40 to 85     3200       VQFN | 72     72VQFN: 100 mm2: 10 x 10 (VQFN | 72)       Pipeline    
ADC32RF83 无样片 3000     Decimating Filter
Ultra High Speed    
14     2     61.1     9.7     66     6400     1.35     JESD204B     -40 to 85     3200       VQFN | 72     72VQFN: 100 mm2: 10 x 10 (VQFN | 72)       Pipeline