ZHCSDZ0B July   2015  – January 2022 TUSB4020BI-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 3.3-V I/O Electrical Characteristics
    6. 7.6 Hub Input Supply Current
    7. 7.7 Power-Up Timing Requirements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Battery Charging Features
      2. 8.3.2 USB Power Management
      3. 8.3.3 Clock Generation
      4. 8.3.4 Power-Up and Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 External Configuration Interface
    5. 8.5 Programming
      1. 8.5.1 One-Time Programmable (OTP) Configuration
      2. 8.5.2 I2C EEPROM Operation
      3. 8.5.3 SMBus Slave Operation
    6. 8.6 Register Maps
      1. 8.6.1 Configuration Registers
        1. 8.6.1.1  ROM Signature Register (offset = 0h) [reset = 0h]
        2. 8.6.1.2  Vendor ID LSB Register (offset = 1h) [reset = 51h]
        3. 8.6.1.3  Vendor ID MSB Register (offset = 2h) [reset = 4h]
        4. 8.6.1.4  Product ID LSB Register (offset = 3h) [reset = 25h]
        5. 8.6.1.5  Product ID MSB Register (offset = 4h) [reset = 80h]
        6. 8.6.1.6  Device Configuration Register (offset = 5h) [reset = 1Xh]
        7. 8.6.1.7  Battery Charging Support Register (offset = 6h) [reset = 0Xh]
        8. 8.6.1.8  Device Removable Configuration Register (offset = 7h) [reset = 0Xh]
        9. 8.6.1.9  Port Used Configuration Register (offset = 8h) [reset = 0h]
        10. 8.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]
        11. 8.6.1.11 Device Configuration Register 2 (offset = Ah)
        12. 8.6.1.12 UUID Registers (offset = 10h to 1Fh)
        13. 8.6.1.13 Language ID LSB Register (offset = 20h)
        14. 8.6.1.14 Language ID MSB Register (offset = 21h)
        15. 8.6.1.15 Serial Number String Length Register (offset = 22h)
        16. 8.6.1.16 Manufacturer String Length Register (offset = 23h)
        17. 8.6.1.17 Product String Length Register (offset = 24h)
        18. 8.6.1.18 Serial Number Registers (offset = 30h to 4Fh)
        19. 8.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)
        20. 8.6.1.20 Product String Registers (offset = 90h to CFh)
        21. 8.6.1.21 Additional Feature Configuration Register (offset = F0h)
        22. 8.6.1.22 Charging Port Control Register (offset = F2h)
        23. 8.6.1.23 Device Status and Command Register (offset = F8h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Crystal Requirements
      2. 9.1.2 Input Clock Requirements
    2. 9.2 Typical Applications
      1. 9.2.1 Upstream Port Implementation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Downstream Port 1 Implementation
      3. 9.2.3 Downstream Port 2 Implementation
      4. 9.2.4 VBUS Power Switch Implementation
      5. 9.2.5 Clock, Reset, and Miscellaneous
      6. 9.2.6 Power Implementation
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply
    2. 10.2 Downstream Port Power
    3. 10.3 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Placement
      2. 11.1.2 Package Specific
      3. 11.1.3 Differential Pairs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

10.1 Power Supply

VDD should be implemented as a single power plane, as should VDD33.

  • The VDD terminals of the TUSB4020BI-Q1 supply 1.1-V (nominal) power to the core of the TUSB4020BI-Q1. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted to account for this or a ferrite bead with low DC resistance (less than 0.05 Ω) can be selected.
  • The VDD33 terminals of the TUSB4020BI-Q1 supply 3.3-V power rail to the I/O of the TUSB4020BI-Q1. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.
  • All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as close to the TUSB4020BI-Q1 power pins as possible with an optimal grouping of two of differing values per pin.