8.1 Overview

The SN65LVDTxx integrates both low-voltage differential signaling (LVDS) line drivers, with a balanced current source design, and LVDS line receivers into a single package. This device operates from a single supply that is nominally 3.3 V, but the supply can be as low as 3 V and as high as 3.6 V. The input to the SN65LVDTxx LVDS drivers is a LVCMOS/LVTTL signal, and the output is a differential signal complying with the LVDS standard (TIA/EIA-644). The input to the SN65LVDTxx LVDS receivers is a differential signal complying with the LVDS Standard (TIA/EIA-644), and the output is a 3.3-V LVCMOS/LVTTL signal. The differential output signal of the SN65LVDTxx LVDS line drivers operates with a signal level of 350 mV, nominally, at a common-mode voltage of 1.2 V. This low differential output voltage results in low electromagnetic interference (EMI). The differential input signal of the SN65LVDTxx LVDS line receivers operates with a signal level of 350 mV, nominally, at a common-mode voltage of 1.2 V. The differential nature of the LVDS outputs and inputs can provide immunity to common-mode coupled signals (noise) that the driven/received signal may experience, along with a low EMI solution.

The SN65LVDTxx can be used to extend asymmetric bidirectional interface buses. The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package, and the SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. The SN65LVDTxx can be used to extend asymmetric bidirectional interface buses, such as Serial peripheral interface (SPI) over LVDS, to achieve long-distance and low-cost SPI communication.

The SN65LVDTxx is primarily used in point-to-point configurations, as seen in Figure 19. This configuration provides a clean signaling environment for the fast edge rates of the SN65LVDTxx and other LVDS components. The SN65LVDTxx should be connected through a balanced media, which could be a standard twisted pair cable, a parallel pair cable, or simply PCB traces to a LVDS receiver. Typically, the characteristic differential impedance of the media is in the range of 100 Ω. The SN65LVDTxx device is intended to drive a 100-Ω transmission line. The 100-Ω termination resistor is selected to match the media and is located as close to the LVDS receiver input pins as possible.