ZHCSIA3C Februray 2017 – May 2018 LMK04832
PRODUCTION DATA.
Figure 17 illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in Figure 15 except that the feedback to the first PLL is driven by a clock output. The PLL2 reference OSCin is not deterministic to the CLKin or feedback clock.