ZHCSQT2 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

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订购信息

7.5.1 Hardware Programming

The device provides the option of programming through hardware mode (pin control) or by software (SPI mode). Hardware programming is selected by floating or grounding the MODE pin. In hardware control mode, the SPI is disabled and the device is configured by setting the programming pins to the desired level. Figure 7-40 and Table 7-16 describe the programming pin and mode functionality. Not all programing options are available in hardware mode. See the SPI ProgrammingHardware ProgrammingHardware ProgrammingSPI Programming section for details of SPI programming.

GUID-20230328-SS0I-P8JC-F19J-3JZQHNGXHSGR-low.svg Figure 7-40 Hardware Programming Mode

The device reads the state of the programming pins one time at each power-up cycle and device reset. The three states are 1, 0 and float. Make sure the desired state of the pins are established prior to power-up cycle or reset events. To read the pins, the device cycles the pins high and low several times through a weak driver. If a float state is detected on a pin, the device drives the pin low to prevent the pin from floating during normal operation. After the pins are read, changes to the pins are not acknowledged until the next power or reset cycle.

Because the device cycles the pins during the read operation, external pin capacitance and leakage current for the float state are limited. In addition, maximum value of external pullup and pulldown resistance values for logic 1 and logic 0 states (if used) are limited. Figure 7-41 shows the pin condition limits. For proper operation, do not tie floated input pins from other devices together.

GUID-20240124-SS0I-4JH8-Z6KK-8R6ZMMNZNKVG-low.svg Figure 7-41 Hardware Programming Pin Conditions

Table 7-16 shows the pin functions of the hardware programming mode.

Table 7-16 Hardware Programming Pins
PIN NO. DESCRIPTION STATE(1) FUNCTION
MODE 54 SPI or hardware programming mode 0 Hardware programming, all buffers on
1 SPI programming, program through SPI
F Hardware programming, all buffers off
CS/SPEED 55 Speed mode 0 Low-speed mode
1 Max-speed mode
F Mid-speed mode
SCLK/FLTR 56 Filter type 0 Wideband filter
1 Low-latency sinc4 filter
F Low-latency sinc4 + sinc1 filter
SDO/OSR1
SDI/OSR0		 2,1 Filter OSR OSR1/OSR0 WIDEBAND FILTER SINC4 FILTER SINC4 + SINC1 FILTER
00 32 12 64
01 64 16 128
0F 128 24 320
10 256 32 640
11 512 64 1280
1F 1024 128 3200
F0 2048 256 6400
F1 4096 1024 12800
FF 4096 4096 32000
GPIO0/TDM 3 Data port TDM 0 No TDM, four or eight data lanes (all DOUTn pins are used)
1 TDM mode, one data lane (DOUT1 pin)
F TDM mode, two data lanes (DOUT1 and DOUT2 pins)
GPIO1/HDR 4 Data-port header 0 24 data bits (only)
1 STATUS header byte + 24 data bits
F STATUS header byte + 24 data bits + CRC byte
  1. F = float state.

Programming options not available in hardware programming mode are assigned register default values. See the Register MapRegister Map section for default values. Table 7-16 shows the hardware programming mode default value deviations from the register default values.

Table 7-17 Hardware Programming Defaults
FUNCTION HARDWARE MODE DEFAULT
Clock mode External clock
Reference range High reference range