ZHCSQT2 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.13 Noise Performance

The ADCs offer four speed modes allowing trade-offs between power consumption, bandwidth, and resolution. The modes are max speed, high speed, mid speed, and low speed, with decreasing levels of device power consumption. The wideband filter offers data rates up to 512kSPS in max-speed mode, 400kSPS in high-speed mode, 200kSPS in mid-speed mode, and 50kSPS in low-speed mode.

The low-latency sinc4 filter offers data rates up to 1.365MSPS in max-speed mode, 1.066MSPS in high-speed mode, 533kSPS in mid-speed mode, and 133kSPS in low-speed mode.

The programmable oversampling ratio (OSR) establishes the output data rate and associated signal bandwidth that in turn determines total noise performance. Increasing the OSR lowers the signal bandwidth and total noise by averaging more samples from the modulator to yield one conversion result.

Table 7-9 through Table 6-5 summarize the noise performance of the filters. Noise performance is illustrated with 1x input range and a 4.096V reference voltage. In comparison, decreasing the reference voltage to 2.5V decreases dynamic range by 4dB (typical). Operation in 2x input range and a 2.5V reference voltage decreases dynamic range by 3dB (typical) compared to the 1x input range and 4.096V reference voltage.

Noise data are the result of the standard deviation (rms) of the conversion data with inputs shorted and biased to the mid-supply voltage. Noise data are representative of typical performance at TA = 25°C. A minimum of 1,000 or 10 seconds of consecutive conversions (whichever occurs first) are used to measure RMS noise (en). Because of the statistical nature of noise, repeated noise measurements yield higher or lower noise results.

Equation 13 converts RMS noise to dynamic range (dB) and Equation 14 converts RMS noise to effective resolution (bits).

Equation 13. Dynamic Range (dB) = 20 · log[FSR / (2 · √2 · en)]
Equation 14. Effective Resolution (bits) = log2(FSR / en)

where:

  • FSR = 2 · VREF (1x input range)
  • FSR = 4 · VREF (2x input range)
  • en = Noise voltage (RMS)

When evaluating ADC noise performance, consider the effect of the external buffer and amplifier noise to the total noise performance. The noise performance of the ADC is evaluated in isolation by selecting the input short test connection of the input multiplexer.

Table 6-1 Wideband Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 32 512 11.1 108.3 19.5
High speed 25.6 400 10.9 108.5 19.5
Mid speed 12.8 200 10.6 108.7 19.6
Low speed 3.2 50 10.4 108.9 19.6
Max speed 32.768 64 256 7.64 111.6 20.0
High speed 25.6 200 7.50 111.7 20.1
Mid speed 12.8 100 7.30 112.0 20.1
Low speed 3.2 25 7.14 112.2 20.1
Max speed 32.768 128 128 5.34 114.7 20.5
High speed 25.6 100 5.25 114.8 20.6
Mid speed 12.8 50 5.07 115.1 20.6
Low speed 3.2 12.5 4.97 115.3 20.7
Max speed 32.768 256 64 3.79 117.7 21.0
High speed 25.6 50 3.72 117.8 21.1
Mid speed 12.8 25 3.58 118.2 21.1
Low speed 3.2 6.25 3.53 118.3 21.1
Max speed 32.768 512 32 2.71 120.6 21.5
High speed 25.6 25 2.67 120.7 21.5
Mid speed 12.8 12.5 2.54 121.2 21.6
Low speed 3.2 3.125 2.47 121.4 21.7
Max speed 32.768 1024 16 1.98 123.3 22.0
High speed 25.6 12.5 1.95 123.4 22.0
Mid speed 12.8 6.25 1.82 124.1 22.1
Low speed 3.2 1.5625 1.79 124.2 22.1
Max speed 32.768 2048 8 1.47 125.9 22.4
High speed 25.6 6.25 1.44 126.1 22.4
Mid speed 12.8 3.125 1.32 126.8 22.6
Low speed 3.2 0.78125 1.28 127.1 22.6
Max speed 32.768 4096 4 1.12 128.3 22.8
High speed 25.6 3.125 1.11 128.3 22.8
Mid speed 12.8 1.5625 0.94 129.8 23.1
Low speed 3.2 0.390625 0.92 130.0 23.1
Table 6-2 Sinc4 Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 12 1365.3 76.3 91.6 16.7
High speed 25.6 1066.6
Mid speed 12.8 533.3
Low speed 3.2 133.33
Max speed 32.768 16 1024 27.3 100.5 18.2
High speed 25.6 800
Mid speed 12.8 400
Low speed 3.2 100
Max speed 32.768 24 682.67 10.4 108.9 19.6
High speed 25.6 533.3
Mid speed 12.8 266.67
Low speed 3.2 66.67
Max speed 32.768 32 512 7.96 111.2 20.0
High speed 25.6 400
Mid speed 12.8 200
Low speed 3.2 50
Max speed 32.768 64 256 5.57 114.3 20.5
High speed 25.6 200
Mid speed 12.8 100
Low speed 3.2 25
Max speed 32.768 128 128 3.90 117.4 21.0
High speed 25.6 100
Mid speed 12.8 50
Low speed 3.2 12.5
Max speed 32.768 256 64 2.80 120.3 21.5
High speed 25.6 50
Mid speed 12.8 25
Low speed 3.2 6.25
Max speed 32.768 512 32 1.98 123.3 22.0
High speed 25.6 25
Mid speed 12.8 12.5
Low speed 3.2 3.125
Max speed 32.768 1024 16 1.40 126.3 22.5
High speed 25.6 12.5
Mid speed 12.8 6.25
Low speed 3.2 1.56
Max speed 32.768 2048 8 0.99 129.3 23.0
High speed 25.6 6.25
Mid speed 12.8 3.125
Low speed 3.2 0.78
Max speed 32.768 4096 4 0.70 132.3 23.5
High speed 25.6 3.125
Mid speed 12.8 1.563
Low speed 3.2 0.39
Table 6-3 Sinc4 + Sinc1 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE (en)
(µVRMS)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 64 256 5.63 114.2 20.5
High speed 25.6 200
Mid speed 12.8 100
Low speed 3.2 25
Max speed 32.768 128 128 3.98 117.2 21.0
High speed 25.6 100
Mid speed 12.8 50
Low speed 3.2 12.5
Max speed 32.768 320 51.2 2.81 120.3 21.5
High speed 25.6 40
Mid speed 12.8 20
Low speed 3.2 5
Max speed 32.768 640 25.6 1.99 123.3 22.0
High speed 25.6 20
Mid speed 12.8 10
Low speed 3.2 2.5
Max speed 32.768 1280 12.8 1.41 126.3 22.5
High speed 25.6 10
Mid speed 12.8 5
Low speed 3.2 1.25
Max speed 32.768 3200 5.12 0.99 129.3 23.0
High speed 25.6 4
Mid speed 12.8 2
Low speed 3.2 0.5
Max speed 32.768 6400 2.56 0.70 132.3 23.5
High speed 25.6 2
Mid speed 12.8 1
Low speed 3.2 0.25
Max speed 32.768 12800 1.28 0.52 134.9 23.9
High speed 25.6 1
Mid speed 12.8 0.5
Low speed 3.2 0.125
Max speed 32.768 32000 0.512 0.39 137.4 24.3
High speed 25.6 0.4
Mid speed 12.8 0.2
Low speed 3.2 0.05
Table 6-4 Sinc3 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(SPS)		 NOISE (en)
(µVRMS) (1)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 26667 614.4 0.29 140.0 24.7
High speed 25.6 480
Mid speed 12.8 240
Low speed 3.2 60
Max speed 32.768 32000 512 0.27 140.6 24.8
High speed 25.6 400
Mid speed 12.8 200
Low speed 3.2 50
(1) Noise data is limited to the 24-bit quantization levels: 4.096V / 223 codes = 0.488μV / code.
Table 6-5 Sinc3 + Sinc1 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(SPS)		 NOISE (en)
(µVRMS) (1)		 DYNAMIC RANGE
(dB)		 EFFECTIVE RESOLUTION
(Bits)
Max speed 32.768 96000 170.6 0.19 143.7 25.3
High speed 25.6 133.3
Mid speed 12.8 66.6
Low speed 3.2 16.6
Max speed 32.768 160000 102.4 0.15 145.7 25.7
High speed 25.6 80
Mid speed 12.8 40
Low speed 3.2 10
(1) Noise data is limited to the 24-bit quantization levels: 4.096V / 223 codes = 0.488μV / code.