The ADS127L14 and ADS127L18 (ADS127L1x) are quad and octal, simultaneous-sampling, delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The devices offer an excellent combination of dc accuracy, ac resolution, and wide signal bandwidth for synchronized, multichannel data acquisition systems. The ADCs are optimized for high resolution with low power consumption.

The Functional Block Diagram describes the device features. The ADS127L1x consist of four and eight independent delta-sigma ADCs. Each ADC has programmable digital filters that provide sample rates up to 512kSPS in wideband filter mode and 1365.3kSPS in low-latency filter mode. Four selectable speed modes allow optimization of signal bandwidth, resolution, and power consumption.

Signal input and positive-reference precharge buffers of each ADC channel reduce the bandwidth and driving requirements of the external buffers. The VCM output is a buffered mid-supply voltage that drives the common-mode voltage of external buffers and gain stages.

The multibit ΔΣ modulator measures the differential input signal, V_IN = (V_AINP – V_AINN), against the differential reference, V_REF = (V_REFP – V_REFN). The modulator produces low-resolution, high-frequency data. Noise shaping of the modulator shifts the quantization noise of the low-resolution data to an out-of-band frequency range where the digital filter removes this noise. The noise remaining within the pass band is low-level thermal noise. The digital filter decimates and filters the modulator to provide high-resolution output data.

The digital filter has two filter modes: low-latency filter (typically used for dc signal measurement) and wideband filter (typically used for ac signal measurement). The low-latency filter is a variable-order sinc filter with filter options for sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1. This filter allows optimization between noise performance, conversion latency, and signal bandwidth. The wideband filter is a multi-tap, linear phase finite impulse response (FIR) filter. This filter provides outstanding frequency response characteristics with low pass-band ripple, narrow transition-band, and high stop-band attenuation. The filters of each ADC channel are programmable to unique data rates (binary related).

The MODE pin selects the mode of device configuration: by hardware pin settings or by the SPI serial interface.

The frame-sync data port outputs conversion data using four or eight data lanes or time division multiplex (TDM) format to reduce the number of data lanes. Daisy-chain multiple devices by routing the DOUT pins to the DIN pins of the chained devices.

The device supports external clock operation for ac or dc applications, and internal oscillator operation intended for dc applications. The START pin simultaneously synchronizes all ADC channels. The RESET pin resets the ADC.

Cyclic redundancy check (CRC) error detection is available for the frame-sync port and SPI port communications. The register map CRC operates continuously in the background to detect unintended changes to the register settings after the initial settings are uploaded. The open-drain ERROR output pin asserts low when an ADC error is detected.

Eight general-purpose input/output (GPIO) pins are available. Two GPIOs have standalone functionality and six GPIO are multiplexed with the frame-sync data port DIN and DOUT pins.

The AVDD1 supply voltage powers the precharge buffers and the input sampling switches. AVDD2 powers the modulator with an internal voltage regulator. The IOVDD supply voltage is the digital I/O voltage and also powers the digital core with a second voltage regulator. The internal regulators reduce overall power consumption and maintain consistent levels of device performance.