产品详细信息

Number of ADC channels 2 Analog inputs 3 Digital audio interface DSP, I2S, L, PCM, R, TDM Control interface I2C Sampling rate (Max) (kHz) 96 ADC SNR (Typ) (dB) 92 Rating Catalog
Number of ADC channels 2 Analog inputs 3 Digital audio interface DSP, I2S, L, PCM, R, TDM Control interface I2C Sampling rate (Max) (kHz) 96 ADC SNR (Typ) (dB) 92 Rating Catalog
DSBGA (YZH) 16 5 mm² 2.28 x 2.199
  • Stereo Audio ADC
    • 92-dBA Signal-to-Noise Ratio
    • Supports ADC Sample Rates From 8 kHz to
      96 kHz
  • Instruction-Programmable Embedded miniDSP
  • Flexible Digital Filtering With RAM Programmable
    Coefficient, Instructions, and Built-In Standard
    Modes
    • Low-Latency IIR Filters for Voice
    • Linear Phase FIR Filters for Audio
    • Additional Programmable IIR Filters for EQ,
      Noise Cancellation, or Reduction
    • Up to 128 Programmable ADC Digital Filter
      Coefficients
  • Three Audio Inputs With Configurable Automatic
    Gain Control (AGC)
    • Programmable in Single-Ended or Fully
      Differential Configurations
    • Can Be Driven Hi-Z for Easy Interoperability
      With Other Audio ICs
  • Low Power Consumption and Extensive Modular
    Power Control:
    • 6-mW Mono Record 8-kHz
    • 11-mW Stereo Record, 8-kHz
    • 10-mW Mono Record, 48-kHz
    • 17-mW Stereo Record, 48-kHz
  • Programmable Microphone Bias
  • Programmable PLL for Clock Generation
  • I2C Control Bus
  • Audio Serial Data Bus Supports I2S, Left/Right-
    Justified, DSP, PCM, and TDM Modes
  • Power Supplies:
    • Analog: 2.6 V–3.6 V.
    • Digital: Core: 1.65 V–1.95 V,
      I/O: 1.1 V–3.6 V
  • 2.24-mm × 2.16-mm NanoFree™ 16-Ball 16-YZH
    Wafer Chip Scale Package (WCSP)
  • APPLICATIONS
    • Wireless Handsets
    • Portable Low-Power Audio Systems
    • Noise Cancellation Systems
    • Front-End Voice or Audio Processor for Digital
      Audio

All other trademarks are the property of their respective owners

  • Stereo Audio ADC
    • 92-dBA Signal-to-Noise Ratio
    • Supports ADC Sample Rates From 8 kHz to
      96 kHz
  • Instruction-Programmable Embedded miniDSP
  • Flexible Digital Filtering With RAM Programmable
    Coefficient, Instructions, and Built-In Standard
    Modes
    • Low-Latency IIR Filters for Voice
    • Linear Phase FIR Filters for Audio
    • Additional Programmable IIR Filters for EQ,
      Noise Cancellation, or Reduction
    • Up to 128 Programmable ADC Digital Filter
      Coefficients
  • Three Audio Inputs With Configurable Automatic
    Gain Control (AGC)
    • Programmable in Single-Ended or Fully
      Differential Configurations
    • Can Be Driven Hi-Z for Easy Interoperability
      With Other Audio ICs
  • Low Power Consumption and Extensive Modular
    Power Control:
    • 6-mW Mono Record 8-kHz
    • 11-mW Stereo Record, 8-kHz
    • 10-mW Mono Record, 48-kHz
    • 17-mW Stereo Record, 48-kHz
  • Programmable Microphone Bias
  • Programmable PLL for Clock Generation
  • I2C Control Bus
  • Audio Serial Data Bus Supports I2S, Left/Right-
    Justified, DSP, PCM, and TDM Modes
  • Power Supplies:
    • Analog: 2.6 V–3.6 V.
    • Digital: Core: 1.65 V–1.95 V,
      I/O: 1.1 V–3.6 V
  • 2.24-mm × 2.16-mm NanoFree™ 16-Ball 16-YZH
    Wafer Chip Scale Package (WCSP)
  • APPLICATIONS
    • Wireless Handsets
    • Portable Low-Power Audio Systems
    • Noise Cancellation Systems
    • Front-End Voice or Audio Processor for Digital
      Audio

All other trademarks are the property of their respective owners

The TLV320ADC3001 device is a low-power, stereo audio analog-to-digital converter (ADC) supporting sampling rates from 8 kHz to 96 kHz with an integrated programmable-gain amplifier providing up to 40-dB analog gain or AGC. A programmable miniDSP is provided for custom audio processing. Front-end input coarse attenuation of 0 dB, –6 dB, or off, is also provided. The inputs are programmable in a combination of single-ended or fully differential configurations. Extensive register-based power control is available via I2C, enabling mono or stereo recording. Low power consumption makes the TLV320ADC3001 ideal for battery-powered portable equipment.

The AGC programs to a wide range of attack (7 ms–1.4 s) and decay (50 ms–22.4 s) times. A programmable noise gate function is included to avoid noise pumping. Low-latency IIR filters optimized for voice and telephony are available, as well as linear-phase FIR filters optimized for audio. Programmable IIR filters are also available and may be used for sound equalization, or to remove noise components. The audio serial bus can be programmed to support I2S, left-justified, right-justified, DSP, PCM, and TDM modes. The audio bus may be operated in either master or slave mode.

A programmable integrated PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

The TLV320ADC3001 device is a low-power, stereo audio analog-to-digital converter (ADC) supporting sampling rates from 8 kHz to 96 kHz with an integrated programmable-gain amplifier providing up to 40-dB analog gain or AGC. A programmable miniDSP is provided for custom audio processing. Front-end input coarse attenuation of 0 dB, –6 dB, or off, is also provided. The inputs are programmable in a combination of single-ended or fully differential configurations. Extensive register-based power control is available via I2C, enabling mono or stereo recording. Low power consumption makes the TLV320ADC3001 ideal for battery-powered portable equipment.

The AGC programs to a wide range of attack (7 ms–1.4 s) and decay (50 ms–22.4 s) times. A programmable noise gate function is included to avoid noise pumping. Low-latency IIR filters optimized for voice and telephony are available, as well as linear-phase FIR filters optimized for audio. Programmable IIR filters are also available and may be used for sound equalization, or to remove noise components. The audio serial bus can be programmed to support I2S, left-justified, right-justified, DSP, PCM, and TDM modes. The audio bus may be operated in either master or slave mode.

A programmable integrated PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

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类型 标题 下载最新的英文版本 日期
* 数据表 TLV320ADC3001 Low-Power Stereo ADC With Embedded miniDSP for Wireless Handsets and Portable Audio 数据表 (Rev. D) 2015年 8月 31日
应用手册 Audio Serial Interface Configurations for Audio Codecs (Rev. A) 2019年 6月 27日
应用手册 Coefficient RAM Access Mechanisms.. (Rev. D) 2012年 1月 25日
应用手册 Audio Serial Interface Configurations for Audio Codecs 2010年 9月 22日
应用手册 Interfacing an I2S Device to an MSP430 Device (Rev. A) 2010年 3月 22日

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Audio CODEC/ADC PLL Calculator

SLAR163.ZIP (487 KB)
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DSBGA (YZH) 16 了解详情

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