ZHCSQO4
December 2022
TPS65220
ADVANCE INFORMATION
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
BUCK1 Converter
6.6
BUCK2, BUCK3 Converter
6.7
General Purpose LDOs (LDO1, LDO2)
6.8
General Purpose LDOs (LDO3, LDO4)
6.9
GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power-Up Sequencing
7.3.2
Power-Down Sequencing
7.3.3
Push Button and Enable Input (EN/PB/VSENSE)
7.3.4
Reset to SoC (nRSTOUT)
7.3.5
Low Voltage Buck Converters (Buck2 and Buck3)
7.3.5.1
Dual Random Spread Spectrum (DRSS)
7.3.6
Linear Regulators (LDO1 through LDO4)
7.3.7
Interrupt Pin (nINT)
7.3.8
PWM/PFM and Low Power Modes (MODE/STBY)
7.3.9
PWM/PFM and Reset (MODE/RESET)
7.3.10
Voltage Select pin (VSEL_SD/VSEL_DDR)
7.3.11
General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
7.3.12
I2C-Compatible Interface
7.3.12.1
Data Validity
7.3.12.2
Start and Stop Conditions
7.3.12.3
Transferring Data
7.4
Device Functional Modes
7.4.1
Modes of Operation
7.4.1.1
OFF State
7.4.1.2
INITIALIZE State
7.4.1.3
ACTIVE State
7.4.1.4
STBY State
7.4.1.5
Fault Handling
7.5
Device Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.2
Documentation Support
9.2.1
Related Documentation
9.3
接收文档更新通知
9.4
支持资源
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
术语表
10
Mechanical, Packaging, and Orderable Information
10.1
Tape and Reel Information
封装选项
机械数据 (封装 | 引脚)
RHB|32
MPQF130D
散热焊盘机械数据 (封装 | 引脚)
RHB|32
QFND676
订购信息
zhcsqo4_oa
1
TPS65220
适用于 ARM
Cortex
-A53 处理器
和 FPGA
的集成电源管理 IC