C2000 ADC (Type-3) Performance Versus ACQPS

C2000™ ADC (Type-3) Performance Versus ACQPS

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1 Introduction

The sample and hold time, otherwise known as the ‘sample window’ time, is the amount of time allotted to charging the internal sampling capacitor of an ADC. Some applications may require a longer or shorter time depending on the drive strength of the external connections along the signal path to the ADC pin. For the F2803x device, the acquisition sample and hold (S+H) window size is configured in the ADCSOCxCTL register, and set to a value represented by one less than the desired number of ADC clock cycles. For example, an ACQPS value set to 28 would indicate 29 ADC clock cycles. Since this value is in terms of ADC clock cycles, it is dependent on the ADC's operational frequency. The F2803x devices have two ADC frequency settings, SYSCLK and SYSCLK/2, configurable through the CLKDIV2EN bit field in the ADCCTL2 register. This usually translates to 60 MHz and 30 MHz, respectively. The conversion time is always 13 ADC clock cycles. Therefore, the total time to process a single conversion of an analog voltage is the sample time plus the conversion time. For specific examples on finding the total processing time, see the TMS320F2803x Technical Reference Manual (TRM).

A smaller ACQPS value allows for more ADC readings within a given time frame in comparison to a larger ACQPS value. However, choosing a smaller ACQPS value may not allow the settling time of the sampling capacitor to stabilize, possibly leading to inaccurate results. Having an insufficient ACQPS value could also lead to cross-talk within sequential readings. Therefore, choosing the correct ACQPS value for a given system design is an important decision. Included in the TRM is a generalized list of non-valid ACQPS values. These values lead to significant variation from the specifications defined in the TMS320F2803x Microcontrollers Data Sheet for ADC performance. Table 1 expands on information provided by the TRM to list valid ACQPS values based on the data acquired in this analysis; these values are optimal ACQPS values that lead to stable ADC operation under all conditions and whose conversion results meet data sheet specifications. Values referred to as non-valid throughout this document are those which fall outside the valid ranges.

The ADC can operate in overlap mode. In this mode, ADC conversions occur at the same time a new voltage is being sampled. By comparison, in non-overlap mode the sample and conversion of the input signal occur sequentially. Since the ACQPS value determines the amount of acquisition and hold time, the distinction between overlap and non-overlap mode impacts the amount of conversions the ADC performs within an application. Thus, this report will analyze both modes independently from one another.

In order to bound the effect of the S+H time on the ADC’s performance, the data sheet minimum, typical, and maximum conditions for operational temperature and analog voltage (VDDA) are discussed within this report in conjunction with the ACQPS setting. Intermediate values of these parameters can be assumed to follow similar trends, but require in-depth analysis for specific system conditions. Efforts were made to ensure the data presented had adequate code spread. For more information regarding this topic, see Section ASection A.1.

2 Offset Error

The offset error of an ADC can be defined as the deviation between the measured and ideal reading, in terms of Least Significant Bits (LSBs), when a 0 volt (V) input is applied to any of the input pins. Usually offset error is adjusted for by correcting it through the OFFTRIM bits in the ADCOFFSETTRIM register. For more detailed information regarding the process of reducing offset error, see the ADC Zero Offset Calibration section in the TMS320F2803x Technical Reference Manual (TRM). Each ACQPS setting needs to be trimmed differently, as each of the values leads to a different offset error under the same system conditions. Also, each start of conversion (SOC) channel can be configured to have a different ACQPS setting. If this is done in an application, then each channel should be calibrated separately.

1. This graph demonstrates offset error for a 3-bit ADC. The same description applies to a 12-bit ADC. FS represents Full Scale.

Figure 1. Offset Error

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 2. Offset Error vs. ACQPS in Overlap Mode

The data sheet specifies ± 20 LSBs of offset error after executing a single self-calibration and ± 4 LSBs for periodic self-recalibration. Figure 2 and Figure 3 show the variation of average offset error among different ACQPS values under nominal conditions with no calibration.

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 3. Offset Error vs. ACQPS in Non-Overlap Mode

Specifically in overlap mode, there are certain ACQPS values that have worse offset error than others. Both in overlap and non-overlap mode, 60MHz can lead to larger negative offset errors particularity for non-valid ACQPS values. Errors from intermediate frequencies between 30 MHz and 60 MHz are not guaranteed to follow the same trends.

As the VDDA supply increases from the minimum supported value to the maximum, the offset error also increases, across non-valid ACQPS settings. The disparity between offset error as it correlates to frequency is also increased when the temperature is lowered to the minimum operational temperature. Therefore, the worst offset error is seen at the lowest operational temperature and the highest operational analog voltage.

As previously mentioned, the offset error can be corrected through calibration. Periodic self calibration is encouraged in order to reduce offset error due to fluctuations in temperature. For software examples on performing periodic self-calibration, or calibrating each SOC differently, see the ADC examples in C2000WARE.

3 Gain Error

The gain error represents the deviation of the ADC’s actual transfer function to the ideal transfer function at the full scale range, maximum input voltage, after the offset error has been nullified. An ideal transfer function of an ADC is one in which the full scale range corresponds to the maximum output code. The F2803x devices have a 12 bit ADC with an internal reference of 3.3 V. For a resolution of 12 bits, the maximum digital output code is 4095. Therefore, in an ideal ADC, 3.3 V would map to a digital reading of 4095. The data sheet for this device family specifies that the gain error for the ADC is within ± 60 LSBs. Under these bounds, the ADC could interpret either 3.252 V (positive gain error) or a value up to 3.348 V (negative gain error) as the maximum output code reading instead of the full scale range. Positive gain error will saturate the converter at an earlier voltage reading; meaning all codes above a certain voltage threshold, depending on the amount of error, will result in the maximum output code.

1. This graph demonstrates gain error for a 3-bit ADC. The same description applies to a 12-bit ADC.

Figure 4. Gain Error

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 5. Gain Error vs. ACQPS Value in Overlap Mode

The gain error fluctuates in relation to ACQPS values when operating in overlap mode. Specifically referencing 30 and 60 MHz, as the operating temperature increases, the gain error range (maximum to minimum error value) also increases. 30 MHz is more susceptible to this change than 60 MHz. However, as temperature decreases, gain error becomes more dependent on the ADC operating frequency. This behavior causes some of the non-valid ACQPS values to have gain errors outside of the data sheet range.

An increase in voltage will shift the gain error down, towards larger negative values. This is however not applicable while operating at the lowest operable temperature because the error range does not shift with changes in VDDA.

Figure 6 shows these descriptions in a graphical form.

1. This graph contains arbitrary gain error values to show an example of how the gain error range changes from the baseline depending on operational temperature and analog voltage.

Figure 6. Gain Error Relationships

In non-overlap mode, input signals are only sampled while the ADC conversion stage is idle. Figure 7 illustrates how the gain error fluctuates in relation to ACQPS values when operating in non-overlap mode under nominal conditions. Much like overlap mode, the gain error range increases with increasing temperatures, solely in regards to 30 and 60 MHz; this shifted error range is still within the specified gain error range of ± 60 LSBs, as it is for all operable temperatures. Different values of VDDA will shift this range towards larger positive or negative gain errors depending on the operational frequency. For temperatures between the typical and maximum operable values, the larger VDDA voltages shift the gain error towards more negative values, as in overlap mode.

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 7. Gain Error vs. ACQPS Value in Non-Overlap Mode

Based on the plots shown above, there are non-valid ACQPS values that have gain error that exceed those limits specified by the data sheet. In order to more closely model the ideal ADC transfer function, ACQPS values that have gain error outside of the data sheet specifications should be avoided as they can lead to an inaccurate representation of the full scale range.

4 Linearity Error

There are two forms of non-linearity: differential (DNL) and integral (INL). Both DNL and INL should be calculated when the gain and offset errors have been nullified in order to get an accurate representation for the ADC’s linearity performance.

1. DNL Error (Left), INL Error (Right). These graphs demonstrate linearity error for a 3-bit ADC. The same description applies to a 12-bit ADC.

Figure 8. Linearity Error