SPRACP5 December   2019 TMS320F2802-Q1 , TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28022-Q1 , TMS320F280220 , TMS320F28023 , TMS320F28023-Q1 , TMS320F280230 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F280270 , TMS320F28027F , TMS320F28027F-Q1 , TMS320F28030 , TMS320F28030-Q1 , TMS320F28031 , TMS320F28031-Q1 , TMS320F28032 , TMS320F28032-Q1 , TMS320F28033 , TMS320F28033-Q1 , TMS320F28034 , TMS320F28034-Q1 , TMS320F28035 , TMS320F28035-EP , TMS320F28035-Q1 , TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052-Q1 , TMS320F28052F , TMS320F28052F-Q1 , TMS320F28052M , TMS320F28052M-Q1 , TMS320F28053 , TMS320F28054 , TMS320F28054-Q1 , TMS320F28054F , TMS320F28054F-Q1 , TMS320F28054M , TMS320F28054M-Q1 , TMS320F28055 , TMS320F2806-Q1 , TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

 

  1.   C2000 ADC (Type-3) Performance Versus ACQPS
    1.     Trademarks
    2. 1 Introduction
    3. 2 Offset Error
    4. 3 Gain Error
    5. 4 Linearity Error
      1. 4.1 Differential Non-Linearity Error
      2. 4.2 Integral Non-Linearity Error
    6. 5 Summary
    7. 6 References
  2.   A DC Code Spread
    1.     A.1 Overview
    2.     A.2 Method
  3.   B Calculating DNL Error
    1.     B.1 Histogram Method

B.1 Histogram Method

This section explains in greater detail how the histogram method is used to calculate DNL error. In this method, a sine wave or ramp function is delivered to the ADC pin. This signal may be filtered or altered to meet additional system requirements and ensure a clean input signal. The ADC should be configured to constantly sample the input signal as the function is swept. After every conversion, a tally is kept corresponding to a certain digital output code; each code represented by a bin. Every time a conversion matches one of the codes, referred to a ‘hit’, the tally for that digital output code is increased by one. Ideally, after one complete period of the input function the tallies for each output code, width size, should be the same indicating no DNL error.

The minimum and maximum output codes are discarded from this analysis since they will skew the data with large number of hits unless the input function is perfectly timed to start and end along with the ADC. Beginning with the first bin, second output code, the DNL error is found using Equation 2; here 'Average Hits' signifies the average number of hits for all the bins excluding those that correspond to the minimum and maximum output codes for the reason previously mentioned.

Equation 2. D N L O u t p u t   C o d e = #   H i t s O u t p u t   C o d e A v e r a g e   H i t s -1

A positive DNL error, larger # of hits than the average, signifies that the respective output code will represent a wider range of voltage than that of 1 LSB. Whereas, a negative DNL error, smaller # of hits than the average, indicates the opposite. For a visual reference, see Figure 14.

spracp5_histogram_method.gif
1. Histogram with all of the output codes (Left), Segmented portion of the Histogram on the left showing missing codes (Right)
Figure 14. Finding DNL: Histogram Method