3 Gain Error

The gain error represents the deviation of the ADC’s actual transfer function to the ideal transfer function at the full scale range, maximum input voltage, after the offset error has been nullified. An ideal transfer function of an ADC is one in which the full scale range corresponds to the maximum output code. The F2803x devices have a 12 bit ADC with an internal reference of 3.3 V. For a resolution of 12 bits, the maximum digital output code is 4095. Therefore, in an ideal ADC, 3.3 V would map to a digital reading of 4095. The data sheet for this device family specifies that the gain error for the ADC is within ± 60 LSBs. Under these bounds, the ADC could interpret either 3.252 V (positive gain error) or a value up to 3.348 V (negative gain error) as the maximum output code reading instead of the full scale range. Positive gain error will saturate the converter at an earlier voltage reading; meaning all codes above a certain voltage threshold, depending on the amount of error, will result in the maximum output code.

1. This graph demonstrates gain error for a 3-bit ADC. The same description applies to a 12-bit ADC.

Figure 4. Gain Error

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 5. Gain Error vs. ACQPS Value in Overlap Mode

The gain error fluctuates in relation to ACQPS values when operating in overlap mode. Specifically referencing 30 and 60 MHz, as the operating temperature increases, the gain error range (maximum to minimum error value) also increases. 30 MHz is more susceptible to this change than 60 MHz. However, as temperature decreases, gain error becomes more dependent on the ADC operating frequency. This behavior causes some of the non-valid ACQPS values to have gain errors outside of the data sheet range.

An increase in voltage will shift the gain error down, towards larger negative values. This is however not applicable while operating at the lowest operable temperature because the error range does not shift with changes in VDDA.

Figure 6 shows these descriptions in a graphical form.

1. This graph contains arbitrary gain error values to show an example of how the gain error range changes from the baseline depending on operational temperature and analog voltage.

Figure 6. Gain Error Relationships

In non-overlap mode, input signals are only sampled while the ADC conversion stage is idle. Figure 7 illustrates how the gain error fluctuates in relation to ACQPS values when operating in non-overlap mode under nominal conditions. Much like overlap mode, the gain error range increases with increasing temperatures, solely in regards to 30 and 60 MHz; this shifted error range is still within the specified gain error range of ± 60 LSBs, as it is for all operable temperatures. Different values of VDDA will shift this range towards larger positive or negative gain errors depending on the operational frequency. For temperatures between the typical and maximum operable values, the larger VDDA voltages shift the gain error towards more negative values, as in overlap mode.

1. Data presented in this figure was acquired under nominal operating conditions.

Figure 7. Gain Error vs. ACQPS Value in Non-Overlap Mode

Based on the plots shown above, there are non-valid ACQPS values that have gain error that exceed those limits specified by the data sheet. In order to more closely model the ideal ADC transfer function, ACQPS values that have gain error outside of the data sheet specifications should be avoided as they can lead to an inaccurate representation of the full scale range.