SPRACK9 February   2019 AM1705 , AM1707 , AM1806 , AM1808 , OMAP-L132 , OMAP-L137 , OMAP-L138 , TMS320C6742 , TMS320C6745 , TMS320C6746 , TMS320C6747 , TMS320C6748

 

  1.   OMAP-L13x/C674x/AM1x schematic review guidelines
    1.     Trademarks
    2. 1 Introduction
    3. 2 Recommendations Specific to OMAP-L1x/TMS320C674x/AM1x
      1. 2.1 EVM vs Data Sheet
      2. 2.2 Before You Begin
        1. 2.2.1 Documentation
        2. 2.2.2 Pinout
      3. 2.3 Critical Connections
        1. 2.3.1 Decoupling capacitors
        2. 2.3.2 Power
        3. 2.3.3 Ground
        4. 2.3.4 Clocking
        5. 2.3.5 Reset
        6. 2.3.6 Boot
        7. 2.3.7 Pin multiplexing
        8. 2.3.8 Debug
      4. 2.4 Peripherals
        1. 2.4.1 UART
        2. 2.4.2 EMAC
        3. 2.4.3 MMC/SD
        4. 2.4.4 EMIF
          1. 2.4.4.1 NAND
          2. 2.4.4.2 NOR
          3. 2.4.4.3 DDR2/mDDR
        5. 2.4.5 SPI
        6. 2.4.6 I2C
        7. 2.4.7 McASP
          1. 2.4.7.1 Audio
        8. 2.4.8 USB
          1. 2.4.8.1 USB0 (USB 2.0 OTG)
          2. 2.4.8.2 USB1 (USB 1.1 OHCI)
          3. 2.4.8.3 Unused USB pins
          4. 2.4.8.4 USB Board Design Guidelines
            1. 2.4.8.4.1 Cautionary note - USB PHY off while host is still powered on
        9. 2.4.9 Other
          1. 2.4.9.1 Signal Visibility
          2. 2.4.9.2 Voltage Level Changes
          3. 2.4.9.3 Signal Terminations
          4. 2.4.9.4 Ground Symbols
          5. 2.4.9.5 Power Symbols
    4. 3 BGA PCB Design
    5. 4 Power Management Solutions
    6. 5 References
  2.   A XDS Connector Design Checklist
    1.     A.1 XDS Connector Design
  3.   B Connecting NOR Flash to OMAP-L138
    1.     B.1 Connecting Memory Devices <32 MB
    2.     B.2 Connecting Memory Devices >32 MB

2.4.8.4.1 Cautionary note - USB PHY off while host is still powered on

When the USB PHY is powered off while still connected to a host that is powered on, the customer may notice leakage on the 3.3 V supply. This is because there is a path between VBUS and the 3.3 V supply rail that allows current to leak from the powered VBUS to the 3.3 V supply rail.

If the USB PHY remains powered off for an indefinite period of time while connected to a powered VBUS, there is a risk of long-term stress on the PHY’s internal circuitry. TI therefore recommends that customers isolate the input USB0_VBUS from the VBUS until the device is powered up. This can be accomplished by implementing a discrete load switch such as TPS22913. Some example circuits are shown in Figure 2 and Figure 3.

If the SoC supports OTG Host/Device mode:

Fig1_OTG.gifFigure 2. Isolation Circuit for OTG Host/Device Mode

If the SoC supports Device-only mode:

Fig2_DeviceOnly.gifFigure 3. Isolation Circuit for Device-Only Mode