产品详情

Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
Arm CPU 1 Arm9 Arm (max) (MHz) 375, 456 Coprocessors PRU-ICSS CPU 32-bit Display type 1 LCD Protocols Ethernet Ethernet MAC 1-Port 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Power supply solution TPS650061 Operating temperature range (°C) -40 to 105
PBGA (ZKB) 256 289 mm² 17 x 17
  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Automotive, or Extended Temperature
  • 375- and 456-MHz ARM926EJ-S™ RISC Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • Single-Cycle MAC
    • ARM Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • 128KB of RAM Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Automotive, or Extended Temperature

The device is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These include C compilers and a Windows® debugger interface for visibility into source code execution.

The device is a low-power ARM microprocessor based on an ARM926EJ-S.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These include C compilers and a Windows® debugger interface for visibility into source code execution.

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类型 标题 下载最新的英语版本 日期
* 数据表 AM1707 ARM® Microprocessor 数据表 (Rev. E) PDF | HTML 2014年 6月 17日
* 勘误表 AM1707 ARM Microprocessor Silicon Errata (Silicon Revisions 3.0, 2.1, and 2.0) (Rev. E) 2014年 6月 17日
* 用户指南 AM1707 ARM Microprocessor Technical Reference Manual (Rev. D) 2016年 9月 22日
用户指南 ARM 优化 C/C++ 编译器 v20.2.0.LTS (Rev. W) PDF | HTML 英语版 (Rev.W) PDF | HTML 2023年 4月 13日
用户指南 ARM 汇编语言工具 v20.2.0.LTS (Rev. Z) PDF | HTML 英语版 (Rev.Z) PDF | HTML 2023年 4月 13日
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
用户指南 ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
用户指南 ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
应用手册 General Hardware Design/BGA PCB Design/BGA 2019年 2月 22日
应用手册 OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 2019年 2月 14日
用户指南 ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
用户指南 ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
用户指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
用户指南 ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
用户指南 ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
用户指南 ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
用户指南 ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
用户指南 ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
用户指南 ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
用户指南 ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
用户指南 ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
应用手册 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015年 8月 13日
用户指南 ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
用户指南 ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
应用手册 Using the AM17xx Bootloader (Rev. C) 2012年 5月 31日
应用手册 Powering the AM1705 and AM1707 With the TPS650061 (Rev. A) 2011年 10月 18日
应用手册 AM17x Power Consumption Summary 2010年 6月 30日
应用手册 AM17xx Pin Multiplexing Utility 2010年 3月 1日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

调试探针

TMDSEMU200-U — XDS200 USB 调试探针

XDS200 是用于调试 TI 嵌入式器件的调试探针(仿真器)。与低成本的 XDS110 和高性能的 XDS560v2 相比,XDS200 在低成本和高性能之间实现了平衡;并在单个仓体中支持广泛的标准(IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 Arm® 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的内核跟踪,则需要使用 XDS560v2 PRO TRACE

XDS200 通过 TI 20 引脚连接器(带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 (...)

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调试探针

TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针

XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。

所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE

XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)

TI.com 上无现货
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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软件开发套件 (SDK)

LINUXEZSDK-SITARA — 用于 Sitara™ ARM® 处理器的 Linux EZ 软件开发套件 (EZSDK)

Linux EZ 软件开发套件 (EZ SDK) 为 Sitara™ 开发人员提供了提供了轻松设置、开包即用的快捷体验(特定于且突出了 Sitara ARM9® 和 Cortex™ -A8® 微处理器的特性)。使用附带的图形用户界面,即可轻松启用演示、基准和应用。Sitara Linux EZ SDK 还可使开发人员快速开始开发其自己的应用,并将其轻松添加至由开发人员定制的应用程序启动器中。
软件开发套件 (SDK)

WINCESDK-AM1XOMAPL1X — 用于 Sitara™ ARM® AM1x /OMAP-L1x 器件的 Windows 嵌入式 CE ™ 软件开发套件 (SDK)

查看 WEP 徽标

 


Microsoft Windows™ 嵌入式 CE* (CE) 6.0 R3 这款操作系统专门针对需要最小存储器(基于组合架构)的嵌入式器件进行了优化。Windows CE 是具有显著特点的内核,它可以在低于 1 兆字节的存储器中运行。它符合实时操作系统的定义,具有确定的中断延迟。专为与 Microsoft 的 Platform Builder 和 Visual Studio 工具配合使用而设计,Windows 嵌入式 CE 6.0 R3 操作系统使开发人员能够使用熟悉的全功能嵌入式设计环境来立即着手开发。通过使用熟悉的标准 Windows 嵌入式 CE 应用编程接口 (...)
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

启动 下载选项
仿真模型

AM1707 ZKB BSDL Model

SPRM492.ZIP (6 KB) - BSDL Model
仿真模型

AM1707 ZKB IBIS Model (Rev. A)

SPRM493A.ZIP (176 KB) - IBIS Model
参考设计

PR1061 — 用 TPS650061 给 AM1705 和 AM1707 供电

Low cost integrated power solution for AM17xx processors
测试报告: PDF
封装 引脚 CAD 符号、封装和 3D 模型
PBGA (ZKB) 256 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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