产品详细信息

Arm CPU 1 Arm9 Arm MHz (Max.) 456 Co-processor(s) C674x DSP CPU 32-bit Display type 1 Protocols Ethernet Ethernet MAC 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Operating temperature range (C) -40 to 125, -40 to 90, -40 to 105, 0 to 90
Arm CPU 1 Arm9 Arm MHz (Max.) 456 Co-processor(s) C674x DSP CPU 32-bit Display type 1 Protocols Ethernet Ethernet MAC 10/100 Hardware accelerators PRUSS Operating system Linux, RTOS Security Device identity, Memory protection Rating Catalog Operating temperature range (C) -40 to 125, -40 to 90, -40 to 105, 0 to 90
BGA (ZKB) 256 289 mm² 17 x 17
  • Software Support
    • TI DSP/BIOS
    • Chip Support Library and DSP Library
  • Dual Core SoC
    • 375- and 456-MHz ARM926EJ-S RISC MPU
    • 375- and 456-MHz C674x VLIW DSP
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM® Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9™ Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature
  • Software Support
    • TI DSP/BIOS
    • Chip Support Library and DSP Library
  • Dual Core SoC
    • 375- and 456-MHz ARM926EJ-S RISC MPU
    • 375- and 456-MHz C674x VLIW DSP
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM® Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9™ Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 OMAP-L137 Low-Power Applications Processor 数据表 (Rev. G) 2014年 6月 17日
* 勘误表 OMAP-L137 C6000 DSP+ARM Processor Errata (Silicon Revs 3.0, 2.1, 2.0, 1.1 & 1.0) (Rev. I) 2014年 6月 17日
* 用户指南 OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) 2016年 9月 21日
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020年 6月 1日
用户指南 ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. Y) 2020年 2月 4日
用户指南 ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. V) 2020年 2月 4日
用户指南 ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. X) 2019年 6月 3日
用户指南 ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. U) 2019年 6月 3日
应用手册 General Hardware Design/BGA PCB Design/BGA Decoupling 2019年 2月 22日
应用手册 OMAP-L13x / C674x / AM1x Schematic Review Checklist 2019年 2月 14日
应用手册 Digital Audio With McASP 2019年 1月 10日
技术文章 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
用户指南 ARM Assembly Language Tools v18.9.0.STS User's Guide (Rev. W) 2018年 11月 19日
用户指南 ARM Optimizing C/C++ Compiler v18.9.0.STS User's Guide (Rev. T) 2018年 11月 19日
应用手册 High-Speed Interface Layout Guidelines (Rev. H) 2018年 10月 11日
技术文章 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
白皮书 Designing professional audio mixers for every scenario 2018年 6月 28日
用户指南 ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. U) 2018年 1月 16日
用户指南 ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. R) 2018年 1月 16日
用户指南 ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. T) 2017年 9月 30日
用户指南 ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. Q) 2017年 9月 30日
用户指南 ARM Assembly Language Tools v17.3.0.STS User's Guide (Rev. S) 2017年 6月 21日
用户指南 ARM Optimizing C/C++ Compiler v17.3.0.STS User's Guide (Rev. P) 2017年 6月 21日
技术文章 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
用户指南 ARM Assembly Language Tools v15.12.0.LTS User's Guide (Rev. P) 2016年 4月 30日
用户指南 ARM Optimizing C/C++ Compiler v15.12.0.LTS User's Guide (Rev. M) 2016年 4月 30日
技术文章 TI's new DSP Benchmark Site 2016年 2月 8日
用户指南 ARM Assembly Language Tools v5.1 User's Guide (Rev. M) 2014年 11月 5日
用户指南 ARM Optimizing C/C++ Compiler v5.1 User's Guide (Rev. J) 2014年 11月 5日
应用手册 USB 2.0 板载设计及布线指南 (Rev. A) 下载最新的英文版本 (Rev.H) 2013年 7月 26日
用户指南 TMS320C6000 Assembly Language Tools v 7.3 User's Guide (Rev. W) 2012年 8月 21日
用户指南 TMS320C6000 Optimizing Compiler v 7.3 User's Guide (Rev. U) 2012年 8月 21日
应用手册 Using the OMAP-L1x7 Bootloader (Rev. G) 2012年 6月 1日
应用手册 Power Sequencing for OMAP-L132, L137, and L138 using the TPS650061 2012年 4月 13日
白皮书 MityDSP®-L138F Software Defined Radio Using uPP Data Transfer (Rev. A) 2012年 2月 2日
应用手册 Power Consumption Guide for the C66x 2011年 10月 6日
用户指南 TMS320C674x/OMAP-L137 Processor Peripherals Overview Reference Guide (Rev. F) 2011年 9月 14日
白皮书 OpenCV on TI’s DSP+ARM® 2011年 7月 27日
白皮书 Middleware/Firmware design challenges due to dynamic raw NAND market 2011年 5月 19日
应用手册 使用离散 DC/DC 转换器和 LDO 的电源解决方案 (Rev. B) 下载英文版本 (Rev.B) 2010年 10月 8日
用户指南 TMS320C674x DSP Megamodule Reference Guide (Rev. A) 2010年 8月 3日
用户指南 TMS320C674x DSP CPU 和指令集用户指南 (Rev. B) 2010年 7月 30日
应用手册 OMAP-L137 Power Consumption Summary 2010年 6月 30日
应用手册 Power Solution using LDO's (Rev. A) 2010年 3月 25日
应用手册 Power Solution using a Dual DCDC Converter and a LDO (Rev. A) 2010年 3月 25日
用户指南 TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 2010年 3月 18日
用户指南 TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 2010年 3月 18日
更多文献资料 OMAP-L1x Software Solutions Diagram (Rev. B) 2009年 12月 7日
应用手册 TMS320C6472 Power-On Self Test 2009年 11月 25日
应用手册 OMAP-L137 TMS320C6747/C6745/C6743 Pin Multiplexing Utility (Rev. A) 2009年 9月 26日
应用手册 OMAP-L137 Complementary Products 2009年 9月 23日
白皮书 Efficient fixed- and floating-point code execution on the TMS320C674x core 2009年 6月 24日
应用手册 TMS320DM674x/OMAP-L1x Universal Bus Downstream Compliance Testing 2009年 3月 12日
应用手册 TMS320DM674x/OMAP-L1x Universal Serial Bus Upstream Device Compliance Testing 2009年 3月 12日
应用手册 TMS320DM67x/OMAP-L1x USB Compliance Checklist 2009年 3月 12日
应用手册 OMAP-L137 Technical Brief (Rev. B) 2009年 2月 18日
用户指南 TMS320C674x DSP Cache User's Guide (Rev. A) 2009年 2月 11日
用户指南 TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 2008年 5月 15日
用户指南 TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 2008年 5月 15日
用户指南 TMS320C6000 Assembly Language Tools v 6.0 Beta User's Guide (Rev. P) 2006年 10月 31日
用户指南 TMS320C6000 Optimizing Compiler v 6.0 Beta User's Guide (Rev. N) 2005年 7月 29日

设计与开发

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TMDSOSKL137 — OMAP-L137/TMS320C6747 浮点入门套件

与 Spectrum Digital Inc. 联合开发的 OMAP-L137/TMS320C6747 浮点入门套件是低成本开发平台,旨在加快基于 TI OMAP-L13x 应用处理器和 TMS320C674x 定点/浮点 DSP(TMS320C6747、TMS320C6745 和 TMS320C6743)的高精度应用的开发速度。该套件使用 USB 通信来真正实现即插即用功能。初级和熟练的设计人员都可以使用该入门套件的全功能 Code Composer StudioTM 集成开发环境 (IDE) 和 eXpressDSPTM 软件(包含 DSP/BIOS™ 内核)立即开始着手创新的产品设计。该套件还包含演示版的 MontaVista Linux Pro 5.0 工具链。

该入门套件 (SK) 包含:
  • 具有 4MB 串行闪存和 64MB SDRAM 的 OMAP-L137/TMS320C6747 EVM
  • Code Composer StudioTM IDE(仅限于在该入门套件上使用)
  • 演示版 MontaVista Pro 5.0 工具(可与该套件的后续版本配合使用)
  • USB 电缆
  • 通用电源
  • AC (...)
现货
数量限制: 1
调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 PC 上运行,还需要 Code Composer Studio™ IDE 许可证。

(...)

现货
数量限制: 3
调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

现货
数量限制: 1
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

现货
数量限制: 1
软件开发套件 (SDK)

PROCESSOR-SDK-OMAPL137 — 适用于 OMAPL137 处理器且支持 TI-RTOS 的处理器 SDK

处理器 SDK(软件开发套件)是统一的软件平台,适用于 TI 嵌入式处理器,设置简单,提供开箱即用的基准测试和演示。处理器 SDK 的所有版本在 TI 的广泛产品系列中保持一致,让开发人员可以无缝地在多种器件之间重用和迁移软件。处理器 SDK 和 TI 的嵌入式处理器解决方案让可扩展平台解决方案的开发变得前所未有地简单。

适用于 OMAP-L137 的处理器 SDK 包括 TI-RTOS 操作系统的各种支持。

RTOS 亮点:

  • TI-RTOS 内核,一种用于 TI 器件的轻量级实时嵌入式操作系统
  • 芯片支持库、驱动程序和基本的板级支持实用程序
  • 经过优化的 C674x 算法库
驱动程序或库

MATHLIB — 用于浮点器件的 DSP 数学函数库

德州仪器 (TI) 数学库是优化的浮点数学函数库,用于使用 TI 浮点器件的 C 编程器。这些例程通常用于计算密集型实时应用,最佳执行速度是这些应用的关键。通过使用这些例程(而不是在现有运行时支持中找到的例程),您可以在无需重写现有代码的情况下获得更快的执行速度。MATHLIB 库包括目前在现有实时支持库中提供的所有浮点数学例程。这些新函数可称为当前实时支持库名称或包含在数学库中的新名称。
驱动程序或库

SPRC121 — TMS320C67x DSP 库

TI C67x DSPLIB 是一个优化的浮点 DSP 函数库,适用于使用 TMS320C67x 器件的 C 编程器。其中包括可调用 C 语言程序、汇编优化的通用信号处理例程。这些例程通常用于计算密集型实时应用,最佳执行速度是这些应用的关键。通过使用这些例程,您的执行速度会比使用标准 ANSI C 语言编写等效代码更快。另外,通过提供即用型 DSP 函数,TI DSPLIB 可以显著缩短 DSP 应用的开发时间。

特性

自适应滤波 相关性 FFT 滤波和转换 数学 矩阵 其他
DSPF_sp_lms DSPF_sp_autocor DSPF_sp_bitrev_cplx DSPF_sp_fir_cplx DSPF_sp_dotp_sqr DSPF_sp_mat_mul DSPF_sp_blk_move
DSPF_dp_lms DSPF_dp_autocor DSPF_sp_cfftr4_dif DSPF_sp_fir_gen DSPF_sp_dotprod DSPF_sp_mat_trans DSPF_sp_blk_eswap16
    (...)
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

驱动程序或库

WIND-3P-VXWORKS-LINUX-OS — Wind River 处理器 VxWorks 和 Linux 操作系统

Wind River 是提供物联网 (IoT) 软件的全球领导者。自 1981 年以来,该公司的技术一直在为全世界最安全的器件提供支持,现在已广泛应用于超过 20 亿产品中。Wind River 提供全面的边缘到云产品系列,并针对这些产品提供世界一流的全球专业服务和备受赞誉的客户支持。Wind River 的 VxWorks 和 Linux 产品支持各种 TI 处理器。

如需了解有关 Wind River 的更多信息,请访问 https://www.windriver.com

由 Wind River Systems 提供
IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ 集成式开发环境 (IDE)

Code Composer Studio؜™ 软件是一个集成开发环境 (IDE),支持 TI 的微控制器 (MCU) 和嵌入式处理器产品组合。Code Composer Studio 软件包含一整套用于开发和调试嵌入式应用的工具。该软件包含了用于优化的 C/C (...)
操作系统 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify application (...)
由 Mentor Graphics Corporation 提供
软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司,提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息,请访问 https://www.adaptivedigital.com
由 Adaptive Digital Technologies, Inc. 提供
软件编解码器

AURO-3P-3DENGINE — Auro Technologies, Auro-3D Engine with Auro-Codec Decoder and Auro-Matic up-mixing

Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.
由 Auro Technologies N.V. 提供
软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发,VOCAL 的模块化软件套件可用于各种各样的 TI DSP 产品。产品具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com
由 VOCAL Technologies, Ltd. 提供
仿真模型

OMAP-L137 ZKB BSDL Model (Rev. B)

SPRM328B.ZIP (19 KB) - BSDL Model
仿真模型

OMAP-L137 ZKB IBIS Model (Rev. A)

SPRM333A.ZIP (176 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
参考设计

PR2084 — 使用 TPS650061 为 OMAP-L132/OMAP-L137/OMAP-L138 供电

此参考设计为 OMAP-L132、OMAP-L137 和 OMAP-L138 处理器提供了一套完整的电源解决方案和低成本离散排序电路。
封装 引脚 下载
BGA (ZKB) 256 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

推荐产品的参数、评估模块或参考设计可能与此 TI 产品相关

支持与培训

视频