SPNA239 September   2019 RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS20206 , TMS570LS20206-EP , TMS570LS20216 , TMS570LS20216-EP , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS3134 , TMS570LS3135 , TMS570LS3137 , TMS570LS3137-EP

 

  1.   HALCoGen Ethernet Driver With lwIP Integration Demo and Active Web Server Demo
    1.     Trademarks
    2. 1 Introduction
    3. 2 Supported Features
    4. 3 Get the Software
    5. 4 Configuring EMAC and MDIO Using HALCoGen GUI for the lwIP Demo
      1. 4.1 RM46x, RM48x and TMS570LSx HDK
      2. 4.2 TMS570LC43x and RM57x HDK
      3. 4.3 RM57x Launchpad (LAUNCHXL2 RM57x)
      4. 4.4 TMS570LC43 Launchpad (LAUNCHXL2 570LC43x)
    6. 5 Additional Changes for Active Web Server Demo
      1. 5.1 HALCoGen Configuration Changes
      2. 5.2 lwIP Port Changes
      3. 5.3 CCS Project Structure
      4. 5.4 Changing the Web Pages Rendered by Web Server
    7. 6 Programming Sequence Using HALCoGen Generated Drivers
    8. 7 Design of lwIP Integration
      1. 7.1 Hardware Abstraction Layer
      2. 7.2 lwIP Interface Layer
      3. 7.3 Hercules Development Network Interface Layer
        1. 7.3.1 Network Device Initialization
        2. 7.3.2 Packet Data Transmission
        3. 7.3.3 Packet Data Reception
      4. 7.4 lwIP Application Layer
      5. 7.5 System Application Layer
    9. 8 Release Folder Structure
    10. 9 Run the Test
      1. 9.1 Hardware Setup
      2. 9.2 Building and Executing the lwIP Demo
      3. 9.3 Building and Executing the Active Web Server Demo
        1. 9.3.1 I/O Control Demo 1
        2. 9.3.2 I/O Control Demo 2

7.3.2 Packet Data Transmission

Packet data transmission takes place inside the linkoutput callback registered with the lwIP stack. This callback is invoked whenever the lwIP stack receives a packet for transmission from the application layer. The pbuf can contain a chain of packet buffers and, hence, the DMA descriptors are properly updated (chained if necessary), with SOP, EOP and length fields. The first DMA descriptor is marked with the EOP and OWNER flags, while only the last is set with the EOP flag. After filling the BD's with the pbuf information, the BD, which corresponds to the SOP, is written to the HEAD descriptor pointer register to start the transmission. Once a packet is transmitted, the EMAC Control Core generates a transmit interrupt. This interrupt is cleared only if the completion pointer is written with the last BD processed. In the interrupt handler, the next BD to process is taken and traversed to reach the BD that corresponds to the end of the packet. This BD, which corresponds to the end of the packet, is written to the completion pointer. After this, the pbuf that corresponds to this packet is freed. Thus, it is made sure that the freeing of pbuf is done only after the packet transmission is complete.