SPNA239 September   2019 RM46L440 , RM46L450 , RM46L830 , RM46L840 , RM46L850 , RM46L852 , RM48L530 , RM48L540 , RM48L730 , RM48L740 , RM48L940 , RM48L950 , RM48L952 , RM57L843 , TMS570LC4357 , TMS570LC4357-EP , TMS570LC4357-SEP , TMS570LS0232 , TMS570LS0332 , TMS570LS0432 , TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS1114 , TMS570LS1115 , TMS570LS1224 , TMS570LS1225 , TMS570LS1227 , TMS570LS20206 , TMS570LS20206-EP , TMS570LS20216 , TMS570LS20216-EP , TMS570LS2124 , TMS570LS2125 , TMS570LS2134 , TMS570LS2135 , TMS570LS3134 , TMS570LS3135 , TMS570LS3137 , TMS570LS3137-EP

 

  1.   HALCoGen Ethernet Driver With lwIP Integration Demo and Active Web Server Demo
    1.     Trademarks
    2. 1 Introduction
    3. 2 Supported Features
    4. 3 Get the Software
    5. 4 Configuring EMAC and MDIO Using HALCoGen GUI for the lwIP Demo
      1. 4.1 RM46x, RM48x and TMS570LSx HDK
      2. 4.2 TMS570LC43x and RM57x HDK
      3. 4.3 RM57x Launchpad (LAUNCHXL2 RM57x)
      4. 4.4 TMS570LC43 Launchpad (LAUNCHXL2 570LC43x)
    6. 5 Additional Changes for Active Web Server Demo
      1. 5.1 HALCoGen Configuration Changes
      2. 5.2 lwIP Port Changes
      3. 5.3 CCS Project Structure
      4. 5.4 Changing the Web Pages Rendered by Web Server
    7. 6 Programming Sequence Using HALCoGen Generated Drivers
    8. 7 Design of lwIP Integration
      1. 7.1 Hardware Abstraction Layer
      2. 7.2 lwIP Interface Layer
      3. 7.3 Hercules Development Network Interface Layer
        1. 7.3.1 Network Device Initialization
        2. 7.3.2 Packet Data Transmission
        3. 7.3.3 Packet Data Reception
      4. 7.4 lwIP Application Layer
      5. 7.5 System Application Layer
    9. 8 Release Folder Structure
    10. 9 Run the Test
      1. 9.1 Hardware Setup
      2. 9.2 Building and Executing the lwIP Demo
      3. 9.3 Building and Executing the Active Web Server Demo
        1. 9.3.1 I/O Control Demo 1
        2. 9.3.2 I/O Control Demo 2

7.3.1 Network Device Initialization

The first step towards bringing up the interface is done as part of the hdkif_init(). This function is called when the network device is registered with the lwIP stack using netif_add. As part of the initialization, the netif output callbacks are registered and hardware initialization, including PHY and DMA initialization, is performed. DMA buffer descriptor (BD) pools are maintained in the CPPI RAM for both TX and RX channels. The descriptor chains are maintained by the "free_head", which points to the next unused/free descriptor in the BD pool, and "active_tail", which points to the last BD in the active queue that has been en-queued to the hardware. The packet buffers (pbuf) are pre-allocated for maximum length and queued in the receive buffer descriptors before the reception begins. For details on pbuf handling by lwIP, see the lwIP documentation under lwip-1.4.1\doc.