SLVUCD4 November   2022 TPS6594-Q1

 

  1.   PDN-2A User's Guide for Powering DRA821 with TPS65941515-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 TO_ACTIVE
      5. 6.3.5 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8References

6.3.5 TO_RETENTION

The C and D triggers, defined by the NSLEEPx bits or pins, trigger the TO_RETENTION sequence. This sequence disables all power rails and GPIOs that are not supplying the retention rails, as described in Figure 3-1. The sequence can be modified using the I2C_7 and I2C_6 bits found in register FSM_I2C_TRIGGERS. These bits need to be set by I2C before a trigger for the retention state occurs. If the I2C_7 bit is set high, the PMIC enters the DDR retention state. If I2C_6 bit is set high, the PMIC enters the GPIO retention state. TO_RETENTION sequence with GPIO and DDR retention is shown in Figure 6-7. If I2C_6 and I2C_7 are set low, the components associated with DDR and GPIO retention do not remain active, as shown in Figure 6-6.

Note: The I2C_6 and I2C_7 bits need to be set or cleared by I2C in the PMIC before a trigger to the retention state occurs. The triggers are not self-clearing and must be maintained during operation.
In addition to the I2C_7, the processor must also configure the EN_DDR_RET_1V1 signal on GPIO6. This signal is included in the Section 3.2 but is not part of the power sequence.

The following PMIC PFSM instructions are executed automatically in the beginning of the power sequence to configure the PMIC:

// Clear NRSTOUT
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFE
// Set SPMI_LP_EN and FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x18 MASK=0xE7

Figure 6-6 TO_RETENTION when I2C_6 and I2C_7 are Low
Figure 6-7 TO_RETENTION when I2C_6 and I2C_7 are High

At the end of the sequence, PMIC sets the LPM_EN and clears the CLKMON_EN and AMUXOUT_EN bits.