SLVUCD4 November   2022 DRA821U , DRA821U-Q1 , TPS6594-Q1

 

  1.   PDN-2A User's Guide for Powering DRA821 with TPS65941515-Q1 PMIC
  2.   Trademarks
  3. 1Introduction
  4. 2Device Versions
  5. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  6. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  7. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Watchdog Settings
  8. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 TO_ACTIVE
      5. 6.3.5 TO_RETENTION
  9. 7Application Examples
    1. 7.1 Moving Between States: ACTIVE and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 GPIO8 and Watchdog
  10. 8References

5.10 Miscellaneous Settings

These settings detail the default configurations of additional settings, such as spread spectrum, PFSM delays, and LDO timeout. All these settings can be changed though I2C after startup.

Table 5-10 Miscellaneous NVM Settings
Register NameField NameTPS65941515-Q1
ValueDescription
PLL_CTRLEXT_CLK_FREQ0x01.1 MHz
CONFIG_1TWARN_LEVEL0x0130C
I2C1_HS0x0

Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code.

I2C2_HS0x0

Standard, fast or fast+ by default, can be set to Hs-mode by Hs-mode controller code.

EN_ILIM_FSM_CTRL0x0

Buck/LDO regulator ILIM interrupts do not affect FSM triggers.

NSLEEP1_MASK0x0NSLEEP1(B) affects FSM state transitions.
NSLEEP2_MASK0x0NSLEEP2(B) affects FSM state transitions.
CONFIG_2BB_CHARGER_EN0x0Disabled
BB_VEOC0x02.5V
BB_ICHR0x0100uA
RECOV_CNT_REG_2RECOV_CNT_THR0xf0xf
BUCK_RESET_REGBUCK1_RESET0x00x0
BUCK2_RESET0x00x0
BUCK3_RESET0x00x0
BUCK4_RESET0x00x0
BUCK5_RESET0x00x0
SPREAD_SPECTRUM_1SS_EN0x0Spread spectrum disabled
SS_DEPTH0x0No modulation
FSM_STEP_SIZEPFSM_DELAY_STEP0xb0xb
LDO_RV_TIMEOUT_ REG_1LDO1_RV_TIMEOUT0xf16ms
LDO2_RV_TIMEOUT0xf16ms
LDO_RV_TIMEOUT_ REG_2LDO3_RV_TIMEOUT0xf16ms
LDO4_RV_TIMEOUT0xf16ms
USER_SPARE_REGSUSER_SPARE_10x00x0
USER_SPARE_20x00x0
USER_SPARE_30x00x0
USER_SPARE_40x00x0
ESM_MCU_MODE_ CFGESM_MCU_EN0x0ESM_MCU disabled.
ESM_SOC_MODE_ CFGESM_SOC_EN0x0ESM_SoC disabled.
RTC_CTRL_2XTAL_EN0x1Crystal oscillator is enabled
LP_STANDBY_SEL0x1

Low Power Standby state is used as STANDBY state (LDOINT is disabled)

FAST_BIST

0x0

Logic and analog BIST is run at BOOT BIST

STARTUP_DEST0x3ACTIVE
XTAL_SEL0x19 pF
PFSM_DELAY_REG_1PFSM_DELAY10x580x58
PFSM_DELAY_REG_2PFSM_DELAY20x9d0x9d
PFSM_DELAY_REG_3PFSM_DELAY30x00x0
PFSM_DELAY_REG_4PFSM_DELAY40x00x0

GENERAL_REG_0

EN_OVP

0x1

OVP Enabled

VSYS_DEAD_LOCK_EN

0x1

Turn off VCCA with external FET in case of VCCA OVP

PFSM_ERR_RESET_DIS

0x0

PFSM_ERR causes reset to logic

DIS_UVLO_OVP_RESET

0x0

UVLO/OVP cause reset to logic

FAST_BOOT_BIST

0x0

LBIST is run during boot BIST

VMON_ABIST_EN

0x1

VMON ABIST enabled

ABIST_ERROR_MASK

0x0

ABIST errors not masked

GENERAL_REG_1

REG_CRC_EN

0x1

Register CRC enabled

FAST_VCCA_OVP

0x0

Slow; 4us deglitch filter enabled