SLVA704 June   2015 INA209 , INA219 , INA220 , INA220-Q1 , INA223 , INA226 , INA226-Q1 , INA228 , INA228-Q1 , INA230 , INA231 , INA233 , INA234 , INA237 , INA237-Q1 , INA238 , INA238-Q1 , INA3221 , INA3221-Q1 , LM8323 , LM8325-1 , LM8327 , LM8328 , LM8330 , LM8333 , LM8335 , OPT3001 , OPT3004 , P82B715 , P82B96 , PCA9306 , PCA9306-Q1 , PCA9515A , PCA9515B , PCA9518 , PCA9534 , PCA9534A , PCA9535 , PCA9536 , PCA9538 , PCA9539 , PCA9543A , PCA9544A , PCA9545A , PCA9546A , PCA9548A , PCA9554 , PCA9554A , PCA9555 , PCA9557 , PCF8574 , PCF8574A , PCF8575 , PCF8575C , TCA4311A , TCA5405 , TCA6408A , TCA6416A , TCA6418E , TCA6424A , TCA6507 , TCA8418 , TCA8418E , TCA8424 , TCA9406 , TCA9509 , TCA9517 , TCA9517A , TCA9534 , TCA9534A , TCA9535 , TCA9538 , TCA9539 , TCA9539-Q1 , TCA9543A , TCA9544A , TCA9545A , TCA9546A , TCA9548A , TCA9554 , TCA9554A , TCA9555 , TCA9617A , TCA9617B , TCA9800 , TCA9801 , TCA9802 , TCA9803

 

  1.   Understanding the I2C Bus
    1.     Trademarks
    2. 1 Electrical Characteristics
      1. 1.1 Open-Drain for Bidirectional Communication
        1. 1.1.1 Open-Drain Pulling Low
        2. 1.1.2 Open-Drain Releasing Bus
    3. 2 I2C Interface
      1. 2.1 General I2C Operation
        1. 2.1.1 START and STOP Conditions
        2. 2.1.2 Repeated START Condition
      2. 2.2 Data Validity and Byte Format
      3. 2.3 Acknowledge (ACK) and Not Acknowledge (NACK)
    4. 3 I2C Data
      1. 3.1 Writing to a Slave On The I2C Bus
      2. 3.2 Reading From a Slave On The I2C Bus

3.2 Reading From a Slave On The I2C Bus

Reading from a slave is very similar to writing, but with some extra steps. In order to read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. Once the slave acknowledges this register address, the master will send a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave will acknowledge the read request, and the master releases the SDA bus, but will continue supplying the clock to the slave. During this part of the transaction, the master will become the master-receiver, and the slave will become the slave-transmitter.

The master will continue sending out the clock pulses, but will release the SDA line, so that the slave can transmit data. At the end of every byte of data, the master will send an ACK to the slave, letting the slave know that it is ready for more data. Once the master has received the number of bytes it is expecting, it will send a NACK, signaling to the slave to halt communications and release the bus. The master will follow this up with a STOP condition.

Figure 9 shows an example of reading a single byte from a slave register.

i2c_read_single_slva704.gifFigure 9. Example I2C Read from Slave Device's Register