SLUUCC4A October   2020  – September 2021 TPS92520-Q1

 

  1.   Trademarks
  2.   General Texas Instruments High Voltage Evaluation (TI HV EMV) User Safety Guidelines
  3. 1Description
    1. 1.1 Typical Applications
    2. 1.2 Warnings
    3. 1.3 Connector Description
  4. 2Performance Specifications
  5. 3Performance Data and Typical Characteristic Curves
    1. 3.1 1.5A CC BUCK SW-Node Voltage Waveform
    2. 3.2 Start-up Waveforms
    3. 3.3 PWM Dimming
  6. 4Schematic, PCB Layout, and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Layout
    3. 4.3 Bill of Materials
  7. 5Software
    1. 5.1 Demonstration Kit Software Installation for LEDMCUEVM-132 Board
      1. 5.1.1 Installation Overview
    2. 5.2 Step-by-Step Installation Instructions
    3. 5.3 Installation Error Recovery
    4. 5.4 Checking for Updates
  8. 6TPS92520EVM-133 Power Up and Operation
    1. 6.1 Power Up and Operation at VINx < 40 V
    2. 6.2 MCU Control Window
    3. 6.3 SPI Command Window
    4. 6.4 Watchdog Window
    5. 6.5 GUI Devices Window
      1. 6.5.1 Channel 1 or 2 Sub-Window: Settings, Measurements, and Faults
      2. 6.5.2 Device Sub-Window: Shared Device Settings, Measurements, Register Info, and Limp Home
    6. 6.6 Limp Home Mode Window
  9. 7Revision History

6.1 Power Up and Operation at VINx < 40 V

To operate the TPS92520EVM-133 with less than 40 V, then J11 must be removed and the VBIAS test point (TP1) needs to be connected to VIN, assuming that it is below 40 V, or can be connected to an external power supply.

Figure 6-2 Input Voltage Selection Circuit Based on Operating Input Voltage
The TPS92520-Q1 can be setup with a resistor divider that sets the UVLO rising and falling. See the TPS92520-Q1 data sheet for additional information. Table 6-1 shows the VUDIM rising and falling specifications from the data sheet. Always check the data sheet to verify no changes have occurred since publication.

Table 6-1 UDIMx and UVLO Specifications

PARAMETER

TEST CONDITIONS

 MIN NOM MAX UNIT

PWM DIMMING and PROGRAMMABLE UVLO INPUT (UDIMx)
VUDIMx(EN) UDIM input threshold sensed inductor current ripple

Rising

1.22

1.27

 V

Falling

 1.075

1.120

 V

The UVLO feature using a resistor divider on UDIM pins is described and outlined in the Figure 6-3 and Equation 1. See the data sheet for additional information.

Figure 6-3 TPS92520-Q1 Diagram for UVLO Rising and Falling
Equation 1. V I N ( R I S E ) = V U D I M ( R I S E ) × R U V 1 + R U V 2 R U V 1
The TPS92520EVM-133 is setup such that each channel has a UVLO rising of 31.5 V. See Figure 6-4.

Figure 6-4 TPS92520EVM-133 UVLO Rising Schematic and Calculations

If the UVLO rising and falling needs to be disabled, then connect UDIM1 (TP2) and UDIM2 (TP14) to V5D. If the TPS92520EVM-133 is to be used below 40 V then see Figure 6-5.

Figure 6-5 Connections for Operating the TPS92520EVM-133 at VINs Less Than 40 V and Having UVLO Disabled
Note that if UDIMx is attached to V5D, then only the internal PWM settings can be used. The other option is to adjust UVLO rising by changing R4 for channel 1 and R17 for channel 2 using the equation for VIN(RISE), which allows using external PWM dimming, see Figure 6-6.

Figure 6-6 Bottom Side of TPS92510EVM-132 With UVLO Resistors of UDIM for Channel 1 and 2