SLUUCC4A October   2020  – September 2021 TPS92520-Q1

 

  1.   Trademarks
  2.   General Texas Instruments High Voltage Evaluation (TI HV EMV) User Safety Guidelines
  3. 1Description
    1. 1.1 Typical Applications
    2. 1.2 Warnings
    3. 1.3 Connector Description
  4. 2Performance Specifications
  5. 3Performance Data and Typical Characteristic Curves
    1. 3.1 1.5A CC BUCK SW-Node Voltage Waveform
    2. 3.2 Start-up Waveforms
    3. 3.3 PWM Dimming
  6. 4Schematic, PCB Layout, and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Layout
    3. 4.3 Bill of Materials
  7. 5Software
    1. 5.1 Demonstration Kit Software Installation for LEDMCUEVM-132 Board
      1. 5.1.1 Installation Overview
    2. 5.2 Step-by-Step Installation Instructions
    3. 5.3 Installation Error Recovery
    4. 5.4 Checking for Updates
  8. 6TPS92520EVM-133 Power Up and Operation
    1. 6.1 Power Up and Operation at VINx < 40 V
    2. 6.2 MCU Control Window
    3. 6.3 SPI Command Window
    4. 6.4 Watchdog Window
    5. 6.5 GUI Devices Window
      1. 6.5.1 Channel 1 or 2 Sub-Window: Settings, Measurements, and Faults
      2. 6.5.2 Device Sub-Window: Shared Device Settings, Measurements, Register Info, and Limp Home
    6. 6.6 Limp Home Mode Window
  9. 7Revision History

1.3 Connector Description

Table 1-1 describes the connectors and Table 1-2 lists the test points on the EVM and how to properly connect, set up, and use the TPS92520EVM-133.

Figure 1-1 shows the connection diagram and the default jumper locations of the TPS92520EVM-133.

GUID-20200810-CA0I-NW6Z-MHGD-F88GVCLSJL1M-low.gifGUID-20200811-CA0I-J4X0-PK73-4R9T66K6Z92K-low.gifFigure 1-1 Connection Diagram of Computer, USB Cable, LEDMCUEVM-132, and TPS92520EVM-133.
Table 1-1 Connector Descriptions
Connector

Function

Description
J3SPI control from the LEDMCUEVM-132J2 and J3 allow attachment for SPI control of the TPS92520-Q1 to the TI LED MCU, part number LEDMCUEVM-132. J3 is connected to the LEDMCUEVM-132. J2 is connected other EVMs used in star or daisy chain configurations.
J2
J9Additional control signals to EVMJ9 and J5 are CAN, UART, GPIO, PWM, and SSN5 signals that come form LEDMCUEVM-132 by J9 and are passed through to other EVMs by J5.
J5
J1

VIN1 and VIN2 connections

J1 configures how VIN1 and VIN2 are connected to each other or to VIN. No jumpers separates VIN1, VIN2, and VIN. A jumper from pins 2 to 4 connects VIN1 to VIN2. Jumpers from pin 1 to 2 and pin 3 to 4 connect VIN1, VIN2, and VIN all together (this setup is the default configuration).
J6

SPI configuration

J6 allow for the ability to setup the hardware into a daisy chain configuration with both a middle device and end device in the chain. The default configuration is a star configuration (pin 1 and 3 are jumpered and pin 2 and 4 are jumpered) where all devices are controlled by an independent SSN signals and must be selected based on J4 settings.
J10V_REG jumperJ10 is a jumper provided to share VREG from LEDMCUEVM-132 with other SPI controlled EVM, in case a digital supply is needed by the EVM, leave this jumper open because an onboard supply is provided on this EVM.

J11

VIN connection to 5V regulator

J11 is loaded by default which allows for VIN to power the 5-V regulator. Removing J11 allow for the connection of the 5-V regulator by external supply to VBIAS test point to do performance testing such as measuring input current of the regulator.

J7UDIM1 jumperJ7 and J8 are jumpers to allow for PWM signals to be applied to the two channels by the UDIM1 and UDIM2. When the jumpers are removed (default configuration) the PWM outputs can be generated from register setting of the TPS92520 or by applying a signal directly to the UDIM pins. If pins 1 and 2 are shunted on J7 and J8 then a non-inverted PWM signals from the LEDMCUEVM-132 controller board is connected to the UDIM pins and controls the PWM dimming via the GUI. When the jumpers are populated from pin 2 to 3 then the PWM signals from LEDMCUEVM-132 are inverted. The PWM signals can be used to disable the associated channels.
J8UDIM2 jumper
J4SSN configuration jumperJ9 allows configuration of the SSN chip select line, when multiple chips on the same SPI bus are used. By default, evaluation module shunt connect pin 7 and 8 of J4, which is SSN0 of the LEDMCUEVM-132. Moving the shunt location changes the SSN that is used.
Table 1-2 Test Points
Test PointDescription
GND (TP15, TP16, TP17, TP18, TP19)Larger metal turrets and test points allow for multiple connection to grounds across the board.
VIN (TP4)The VIN test point allows for voltage and current measurement of the external power supply applied to the evaluation board for the 5V regulator assuming J1 is configured properly.
VIN1 (TP3)The VIN1 test point allows for voltage and current measurement of the power applied to the VIN1 pin of the TPS92520-Q1 assuming J1 is configured properly.

VIN2 (TP5)

The VIN2 test point allows for voltage and current measurement of the power applied to the VIN2 pin of the TPS92520-Q1 assuming J1 is configured properly.
LHI (TP8)The LHI test point is the LED current reference set point for both Limp-home and standalone mode for the TPS92520-Q1. Setting voltages below 148 mV disables both channels and setting the voltage above 200mV enables both channels in limp home and standalone mode.
nFLT (TP7)The nFLT test point can be used to monitor if a fault has occurrence in the TPS92520-Q1. When a fault occurs, nFLT voltage level goes low. Read Faults and Diagnostics section of the TPS92520-Q1 data sheet to determine which faults trigger the nFLT indication and how to clear the fault.
VLED1 (TP6)The VLED1 test point allows for connection of the LED loads to channel-1 output. Large turrets allow for multiple connections for voltage measurements.
VLED2 (TP12)The VLED2 test point allows for connection of the LED loads to channel-2 output. Large turrets allow for multiple connections for voltage measurements.

SW1 (TP9)

The SW1 test point allows for observing the switch node for channel 1 during operation with an oscilloscope.

SW2 (TP13)

The SW2 test point allows for observing the switch node for channel 2 during operation with an oscilloscope.

VBIAS (TP1)

VBIAS test point connects directly to the input of the linear regulator that generates the 5V supply used by the TPS92520-Q1. The test point can be used to monitor the input voltage or used to connect to an external supply for both voltage and current measurements assuming J11 is unloaded.

5VD (TP10)

5VD test point connects directly to the V5D digital pin of the TPS92520-Q1. This test point can be used to monitor the voltage or used to supply the power directly to the V5D pin assuming J11 is disconnected and nothing is powering the 5V bus. Note if doing current measurements then R10 connects 5VD rail to V5A which consumes power but can be separated by removing R10 and supply V5A externally.

V5A (TP11)

V5A test point connects directly to V5A pin of the TPS92520-Q1. This test point can be used to monitor the voltage or current used to supply the power directly to V5A pin assuming R10 has been removed. By default V5D and V5A are shorted together and the supply is provided by the 5VD supply.

UDIM1 (TP2)

UDIM1 test point allows for the direct connection of the UDIM1 pin of the TPS92520-Q1. UDIM1 test point allows for external PWM dimming signals to control channel 1 assuming J7 is unloaded. This test point can also be used to monitor the PWM signal generated from the LEDMCUEVM-132 for channel 1 assuming J7 is loaded.

UDIM2 (TP14)

UDIM2 test point allows for the direct connection of the UDIM2 pin of the TPS92520-Q1. UDIM2 test point allows for external PWM dimming signals to control channel 2 assuming J8 is unloaded. This test point can also be used to monitor the PWM signal generated from the LEDMCUEVM-132 for channel 2 assuming J8 is loaded.