SLAU923B June   2025  â€“ April 2026 MSPM0H3216 , MSPM0H3216-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Fast Boot
      3. 1.4.3 NONMAIN Layout Types
      4. 1.4.4 NONMAIN_TYPED Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 Peripheral Enable
        1. 2.2.5.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Shutdown Mode Handling (if present)
      7. 2.4.7  Configuration Lockout
      8. 2.4.8  System Status
      9. 2.4.9  Error Handling
      10. 2.4.10 SYSCTL Events
        1. 2.4.10.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.10.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL_H3215_H3216 Registers
    6. 2.6 Quick Start Reference
      1. 2.6.1 Default Device Configuration
      2. 2.6.2 Leveraging MFCLK
      3. 2.6.3 Optimizing Power Consumption in STOP Mode
      4. 2.6.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.6.5 Increasing MCLK Precision
      6. 2.6.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.6.7 Optimizing for Lowest Wakeup Latency
      8. 2.6.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10ADC
    1. 10.1 ADC Overview
    2. 10.2 ADC Operation
      1. 10.2.1  ADC Core
      2. 10.2.2  Voltage Reference Options
      3. 10.2.3  Generic Resolution Modes
      4. 10.2.4  Hardware Averaging
      5. 10.2.5  ADC Clocking
      6. 10.2.6  Common ADC Use Cases
      7. 10.2.7  Power Down Behavior
      8. 10.2.8  Sampling Trigger Sources and Sampling Modes
        1. 10.2.8.1 AUTO Sampling Mode
        2. 10.2.8.2 MANUAL Sampling Mode
      9. 10.2.9  Sampling Period
      10. 10.2.10 Conversion Modes
      11. 10.2.11 Data Format
      12. 10.2.12 Advanced Features
        1. 10.2.12.1 Window Comparator
        2. 10.2.12.2 DMA and FIFO Operation
        3. 10.2.12.3 Analog Peripheral Interconnection
      13. 10.2.13 Status Register
      14. 10.2.14 ADC Events
        1. 10.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 10.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 10.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 10.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 10.3 ADC12 Registers
  13. 11VREF
    1. 11.1 VREF Overview
    2. 11.2 VREF Operation
      1. 11.2.1 Internal Reference Generation
      2. 11.2.2 External Reference Input
      3. 11.2.3 Analog Peripheral Interface
    3. 11.3 VREF Registers
  14. 12UART
    1. 12.1 UART Overview
      1. 12.1.1 Purpose of the Peripheral
      2. 12.1.2 Features
      3. 12.1.3 Functional Block Diagram
    2. 12.2 UART Operation
      1. 12.2.1 Clock Control
      2. 12.2.2 Signal Descriptions
      3. 12.2.3 General Architecture and Protocol
        1. 12.2.3.1  Transmit Receive Logic
        2. 12.2.3.2  Bit Sampling
        3. 12.2.3.3  Majority Voting Feature
        4. 12.2.3.4  Baud Rate Generation
        5. 12.2.3.5  Data Transmission
        6. 12.2.3.6  Error and Status
        7. 12.2.3.7  Local Interconnect Network (LIN) Support
          1. 12.2.3.7.1 LIN Responder Transmission Delay
        8. 12.2.3.8  Flow Control
        9. 12.2.3.9  Idle-Line Multiprocessor
        10. 12.2.3.10 9-Bit UART Mode
        11. 12.2.3.11 RS-485 Support
        12. 12.2.3.12 DALI Protocol
        13. 12.2.3.13 Manchester Encoding and Decoding
        14. 12.2.3.14 IrDA Encoding and Decoding
        15. 12.2.3.15 ISO7816 Smart Card Support
        16. 12.2.3.16 Address Detection
        17. 12.2.3.17 FIFO Operation
        18. 12.2.3.18 Loopback Operation
        19. 12.2.3.19 Glitch Suppression
      4. 12.2.4 Low Power Operation
      5. 12.2.5 Reset Considerations
      6. 12.2.6 Initialization
      7. 12.2.7 Interrupt and Events Support
        1. 12.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 12.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 12.2.8 Emulation Modes
    3. 12.3 UART Registers
  15. 13SPI
    1. 13.1 SPI Overview
      1. 13.1.1 Purpose of the Peripheral
      2. 13.1.2 Features
      3. 13.1.3 Functional Block Diagram
      4. 13.1.4 External Connections and Signal Descriptions
    2. 13.2 SPI Operation
      1. 13.2.1 Clock Control
      2. 13.2.2 General Architecture
        1. 13.2.2.1 Chip Select and Command Handling
          1. 13.2.2.1.1 Chip Select Control
          2. 13.2.2.1.2 Command Data Control
        2. 13.2.2.2 Data Format
        3. 13.2.2.3 Delayed data sampling
        4. 13.2.2.4 Clock Generation
        5. 13.2.2.5 FIFO Operation
        6. 13.2.2.6 Loopback mode
        7. 13.2.2.7 DMA Operation
        8. 13.2.2.8 Repeat Transfer mode
        9. 13.2.2.9 Low Power Mode
      3. 13.2.3 Protocol Descriptions
        1. 13.2.3.1 Motorola SPI Frame Format
        2. 13.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 13.2.4 Reset Considerations
      5. 13.2.5 Initialization
      6. 13.2.6 Interrupt and Events Support
        1. 13.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 13.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 13.2.7 Emulation Modes
    3. 13.3 SPI Registers
  16. 14I2C
    1. 14.1 I2C Overview
      1. 14.1.1 Purpose of the Peripheral
      2. 14.1.2 Features
      3. 14.1.3 Functional Block Diagram
      4. 14.1.4 Environment and External Connections
    2. 14.2 I2C Operation
      1. 14.2.1 Clock Control
        1. 14.2.1.1 Clock Select and I2C Speed
        2. 14.2.1.2 Clock Startup
      2. 14.2.2 Signal Descriptions
      3. 14.2.3 General Architecture
        1. 14.2.3.1  I2C Bus Functional Overview
        2. 14.2.3.2  START and STOP Conditions
        3. 14.2.3.3  Data Format with 7-Bit Address
        4. 14.2.3.4  Data Format with 10-Bit Address
        5. 14.2.3.5  Acknowledge
        6. 14.2.3.6  Repeated Start
        7. 14.2.3.7  SCL Clock Low Timeout
        8. 14.2.3.8  Clock Stretching
        9. 14.2.3.9  Dual Address
        10. 14.2.3.10 Arbitration
        11. 14.2.3.11 Multiple Controller Mode
        12. 14.2.3.12 Glitch Suppression
        13. 14.2.3.13 FIFO operation
          1. 14.2.3.13.1 Flushing Stale Tx Data in Target Mode
        14. 14.2.3.14 Loopback mode
        15. 14.2.3.15 Burst Mode
        16. 14.2.3.16 DMA Operation
        17. 14.2.3.17 Low-Power Operation
      4. 14.2.4 Protocol Descriptions
        1. 14.2.4.1 I2C Controller Mode
          1. 14.2.4.1.1 Controller Configuration
          2. 14.2.4.1.2 Controller Mode Operation
          3. 14.2.4.1.3 Read On TX Empty
        2. 14.2.4.2 I2C Target Mode
          1. 14.2.4.2.1 Target Mode Operation
      5. 14.2.5 Reset Considerations
      6. 14.2.6 Initialization
      7. 14.2.7 Interrupt and Events Support
        1. 14.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 14.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 14.2.8 Emulation Modes
    3. 14.3 I2C Registers
  17. 15CRC
    1. 15.1 CRC Overview
      1. 15.1.1 CRC16-CCITT
    2. 15.2 CRC Operation
      1. 15.2.1 CRC Generator Implementation
      2. 15.2.2 Configuration
        1. 15.2.2.1 Bit Order
        2. 15.2.2.2 Byte Swap
        3. 15.2.2.3 Byte Order
        4. 15.2.2.4 CRC C Library Compatibility
    3. 15.3 CRCP0 Registers
  18. 16Temperature Sensor
  19. 17Timers (TIMx)
    1. 17.1 TIMx Overview
      1. 17.1.1 TIMG Overview
        1. 17.1.1.1 TIMG Features
        2. 17.1.1.2 Functional Block Diagram
      2. 17.1.2 TIMA Overview
        1. 17.1.2.1 TIMA Features
        2. 17.1.2.2 Functional Block Diagram
      3. 17.1.3 TIMx Instance Configuration
    2. 17.2 TIMx Operation
      1. 17.2.1  Timer Counter
        1. 17.2.1.1 Clock Source Select and Prescaler
          1. 17.2.1.1.1 Internal Clock and Prescaler
          2. 17.2.1.1.2 External Signal Trigger
        2. 17.2.1.2 Repeat Counter (TIMA only)
      2. 17.2.2  Counting Mode Control
        1. 17.2.2.1 One-shot and Periodic Modes
        2. 17.2.2.2 Down Counting Mode
        3. 17.2.2.3 Up/Down Counting Mode
        4. 17.2.2.4 Up Counting Mode
        5. 17.2.2.5 Phase Load (TIMA only)
      3. 17.2.3  Capture/Compare Module
        1. 17.2.3.1 Capture Mode
          1. 17.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 17.2.3.1.1.1 CCP Input Edge Synchronization
            2. 17.2.3.1.1.2 CCP Input Pulse Conditions
            3. 17.2.3.1.1.3 Counter Control Operation
            4. 17.2.3.1.1.4 CCP Input Filtering
            5. 17.2.3.1.1.5 Input Selection
          2. 17.2.3.1.2 Use Cases
            1. 17.2.3.1.2.1 Edge Time Capture
            2. 17.2.3.1.2.2 Period Capture
            3. 17.2.3.1.2.3 Pulse Width Capture
            4. 17.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 17.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 17.2.3.1.3.1 QEI With 2-Signal
            2. 17.2.3.1.3.2 QEI With Index Input
            3. 17.2.3.1.3.3 QEI Error Detection
          4. 17.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 17.2.3.2 Compare Mode
          1. 17.2.3.2.1 Edge Count
      4. 17.2.4  Shadow Load and Shadow Compare
        1. 17.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 17.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 17.2.5  Output Generator
        1. 17.2.5.1 Configuration
        2. 17.2.5.2 Use Cases
          1. 17.2.5.2.1 Edge-Aligned PWM
          2. 17.2.5.2.2 Center-Aligned PWM
          3. 17.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 17.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 17.2.5.3 Forced Output
      6. 17.2.6  Fault Handler (TIMA only)
        1. 17.2.6.1 Fault Input Conditioning
        2. 17.2.6.2 Fault Input Sources
        3. 17.2.6.3 Counter Behavior With Fault Conditions
        4. 17.2.6.4 Output Behavior With Fault Conditions
      7. 17.2.7  Synchronization With Cross Trigger
        1. 17.2.7.1 Main Timer Cross Trigger Configuration
        2. 17.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 17.2.8  Low Power Operation
      9. 17.2.9  Interrupt and Event Support
        1. 17.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 17.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 17.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 17.2.10 Debug Handler (TIMA Only)
    3. 17.3 TIMx Registers
  20. 18Low Frequency Subsystem (LFSS_B)
    1. 18.1 Overview
    2. 18.2 Clock System
    3. 18.3 LFSS Reset
    4. 18.4 Real Time Counter (RTC_x)
    5. 18.5 Independent Watchdog Timer (IWDT)
    6. 18.6 Lock Function of RTC and IWDT
    7. 18.7 LFSS Registers
  21. 19RTC
    1. 19.1 Overview
      1. 19.1.1 RTC Instances
    2. 19.2 Basic Operation
    3. 19.3 Configuration
      1. 19.3.1  Clocking
      2. 19.3.2  Reading and Writing to RTC Peripheral Registers
      3. 19.3.3  Binary vs. BCD
      4. 19.3.4  Leap Year Handling
      5. 19.3.5  Calendar Alarm Configuration
      6. 19.3.6  Interval Alarm Configuration
      7. 19.3.7  Periodic Alarm Configuration
      8. 19.3.8  Calibration
        1. 19.3.8.1 Crystal Offset Error
          1. 19.3.8.1.1 Offset Error Correction Mechanism
        2. 19.3.8.2 Crystal Temperature Error
          1. 19.3.8.2.1 Temperature Drift Correction Mechanism
      9. 19.3.9  RTC Prescaler Extension
      10. 19.3.10 RTC Timestamp Capture
      11. 19.3.11 RTC Events
        1. 19.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 19.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 19.4 RTC Registers
  22. 20IWDT
    1. 20.1 542
    2. 20.2 IWDT Clock Configuration
    3. 20.3 IWDT Period Selection
    4. 20.4 Debug Behavior of the IWDT
    5. 20.5 IWDT Registers
  23. 21Window Watchdog Timer (WWDT)
    1. 21.1 WWDT Overview
      1. 21.1.1 Watchdog Mode
      2. 21.1.2 Interval Timer Mode
    2. 21.2 WWDT Operation
      1. 21.2.1 Mode Selection
      2. 21.2.2 Clock Configuration
      3. 21.2.3 Low-Power Mode Behavior
      4. 21.2.4 Debug Behavior
      5. 21.2.5 WWDT Events
        1. 21.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 21.3 WWDT Registers
  24. 22Debug
    1. 22.1 DEBUGSS Overview
      1. 22.1.1 Debug Interconnect
      2. 22.1.2 Physical Interface
      3. 22.1.3 Debug Access Ports
    2. 22.2 DEBUGSS Operation
      1. 22.2.1 Debug Features
        1. 22.2.1.1 Processor Debug
          1. 22.2.1.1.1 Breakpoint Unit (BPU)
          2. 22.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 22.2.1.2 Peripheral Debug
        3. 22.2.1.3 EnergyTrace Technology
      2. 22.2.2 Behavior in Low Power Modes
      3. 22.2.3 Restricting Debug Access
      4. 22.2.4 Mailbox (DSSM)
        1. 22.2.4.1 DSSM Events
          1. 22.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 22.2.4.2 Reference
    3. 22.3 DEBUGSS Registers
  25. 23Revision History
14.2.4.2.1 Target Mode Operation

I2C Target Initialization

  1. Configure SDA and SCL pin functions and select as input by using the IOMUX registers.
  2. Reset the peripheral using I2Cx.RSTCTL register
  3. Enable the power to peripheral using I2Cx.PWREN register
  4. Select and configure the I2C clock using the CLKCTL and CLKDIV registers.
  5. Configure at least one target address by writing the 7-bit address to I2Cx.SOAR register. The additional target address can be enabled and configured by using I2Cx.SOAR2 register.
  6. Enable desired interrupts and/or DMA event by using CPU_INT.IMASK register.
  7. The general call response can be enabled by setting the GENCALL bit in I2Cx.SCTR register.
  8. Enable the I2C target mode by setting the ACTIVE bit in I2Cx.SCTR register.

I2C Target Status

User can read the I2Cx.SSR register to check the current state of the I2C target.

Table 14-13 Target Status Register
Bit FieldDescription
RREQThis bit is set if the I2C controller has outstanding receive data from the I2C controller and is using clock stretching to delay the controller until the data has been read from the SRXDATA FIFO (Target RX FIFO is full)
TREQThis bit is set if the I2C controller has been addressed as a target transmitter and is using clock stretching to delay the controller until data has been written to the STXDATA FIFO (Target TX FIFO is empty).
OAR2SELThis bit is set if SOAR2.OAR2 address matched and ACKed by the target.
QCMDSTQuick command status value. This bit is 0 if the last transaction was a normal transaction or a transaction has not occurred. This bit is set if the last transaction was a quick command transaction
QCMDRWQuick command read / write status. This bit only has meaning when the QCMDST bit is set. This bit is 0 if quick command was a write. This bit is set if quick command was a read.
I2C Target Receiver Mode

Target receiver mode is entered when the target address transmitted by the controller matches its own address and a cleared R/W bit is received. In target receiver mode, serial data bits received on SDA are shifted in with the clock pulses that are generated by the controller device. The target device does not generate the clock, but it can hold SCL low if intervention of the CPU is required after a byte has been received.

After the a data byte is received, the SRXDONE (0x11) interrupt in CPU_INT.IIDX register is set to indicate that a byte has been received. The I2C module automatically acknowledges the received data or user can choice to manually send acknowledge after each byte received by configuring the I2Cx.SACKCTL register.

When the controller generates a START condition, the SSTART (0x17) interrupt in CPU_INT.IIDX register is set. When the controller generates a STOP condition, the SSTOP (0x18) interrupt in CPU_INT.IIDX register is set.

User can also set use the SRXFIFOTRG (0x13) interrupt in CPU_INT.IIDX register to read the data from the receive FIFO. This interrupt will trigger when receive FIFO contains >= defined bytes, the trigger level can be defined by using RXTRIG bit in I2Cx.SFIFOCTL register.

The SRXDONE approach could be used if target wants to slow down communication to evaluate reception of every byte, while the SRXFIFOTRG approach could be used to maximize throughput and avoid clock stretching.

The flow chart of using SRXDONE and SRXFIFOTRG interrupt to read the receive data are shown in Figure 14-16 and Figure 14-17 respectively.
MSPM0H3215 MSPM0H3216 Target Receiver Mode using SRXDONE and ACK override Figure 14-16 Target Receiver Mode using SRXDONE and ACK override
MSPM0H3215 MSPM0H3216 Target Receiver Mode using SRXFIFOTRG and automatic ACKFigure 14-17 Target Receiver Mode using SRXFIFOTRG and automatic ACK

I2C Target Transmitter Mode

Target transmitter mode is entered when the target address transmitted by the controller is identical to its own address with a set R/W bit. The target transmitter shifts the serial data out on SDA with the clock pulses that are generated by the controller device. The target device does not generate the clock, but it can hold SCL low if intervention of the CPU is required after a byte has been transmitted.

After a data byte is transmitted, the STXDONE (0x12) interrupt in CPU_INT.IIDX register is set to indicate that a byte has been transmitted.

When the controller generates a START condition, the SSTART (0x17) interrupt in CPU_INT.IIDX register is set. When the controller generates a STOP condition, the SSTOP (0x18) interrupt in CPU_INT.IIDX register is set.

User can also set use the STXFIFOTRG (0x14) interrupt in CPU_INT.IIDX register to load the data to the transmit FIFO. This interrupt will trigger when transmit FIFO contains <= defined bytes, the trigger level can be defined by using TXTRIG bit in I2Cx.SFIFOCTL register.

The STXDONE approach could be used if target wants to slow down communication to evaluate reception of every byte, while the STXFIFOTRG approach could be used to maximize throughput and avoid clock stretching.

The flow chat of using STXDONE and STXFIFOTRG interrupt to transmit data are shown in Figure 14-18 and Figure 14-19.

MSPM0H3215 MSPM0H3216 Target Transmitter Mode using STXDONEFigure 14-18 Target Transmitter Mode using STXDONE
MSPM0H3215 MSPM0H3216 Target Transmitter Mode using STXFIFOTRG Figure 14-19 Target Transmitter Mode using STXFIFOTRG