SLAA870 February   2019 AFE7422 , AFE7444

 

  1.   Evaluating the frequency hopping capability of the AFE74xx
    1.     Trademarks
    2. 1 Introduction
    3. 2 Phase Coherency vs Phase Continuity
    4. 3 AFE74xx Architecture
      1. 3.1 AFE74xx Receivers: Multiband DDC
      2. 3.2 AFE74xx Transmitters: Multiband DUC
      3. 3.3 Numerically Controlled Oscillator (NCO)
        1. 3.3.1 Programming the NCO frequency
          1. 3.3.1.1 Example: Programming NCO to 1700MHz
        2. 3.3.2 Direct Digital Synthesis (DDS) Mode
    5. 4 Frequency Hopping Methods
      1. 4.1 Maintaining Phase Continuity
        1. 4.1.1 Phase Continuous Hop Time
          1. 4.1.1.1 Serial Peripheral Interface (SPI)
          2. 4.1.1.2 Test Setup
          3. 4.1.1.3 Software Configuration
          4. 4.1.1.4 Test Results
      2. 4.2 Maintaining Phase Coherency
        1. 4.2.1 TX NCO Hopping Using SPI
          1. 4.2.1.1 TX NCO Switch Using SPI Hop Time
            1. 4.2.1.1.1 Software Configuration
            2. 4.2.1.1.2 Test Results
          2. 4.2.1.2 AFE74xx DAC Settling Time
            1. 4.2.1.2.1 Hardware Setup
            2. 4.2.1.2.2 Software Configuration
            3. 4.2.1.2.3 Test Results
        2. 4.2.2 RX NCO Hopping Using the GPIO Pins
          1. 4.2.2.1 Test Setup
          2. 4.2.2.2 Software Configuration
          3. 4.2.2.3 Test Results
    6. 5 NCO Frequency Resolution Versus Hop Time
    7. 6 Fast Frequency Hopping With the Load and Switch
    8. 7 Register Addresses
    9. 8 References

4.1.1.4 Test Results

Figure 14 shows the oscilloscope shot that displays the frequency hop time from 10 MHz to 100 MHz when updating a single NCO. Channel 1 of the oscilloscope is connected to the DAC A output, and is shown as the yellow signal. Channel 2 is connected to the SPIEN pin, which initiates the beginning of every SPI write, and is shown as the blue signal. As seen in the oscilloscope shot, frequency hopping from 10 MHz to 100 MHz using a single TX NCO requires a little less than 4 µs with a SPI clock of approximately 40 MHz. The default SPI clock on the AFE74xxEVM is much slower.

updating-the-frequency-in-one-NCO-takes-about-4_6-us.gifFigure 14. Updating the Frequency in One NCO Requires Approximately 4.6 µs

In Figure 14, the last two de-assertions made by the blue SDEN signal are the SPI writes responsible for toggling and resetting the NCO, and require approximately 1.2 µs to complete.

In the case where multichip synchronization is desired for frequency hopping, multiple NCOs can be reset and updated simultaneously by using SYSREF instead of the SPI. Issuing SYSREF after the NCO frequencies are reprogrammed resets and updates all NCOs simultaneously in order to provide synchronous frequency hopping. Issuing SYSREF requires a single SPI write to the LMK04828 clocking chip. Figure 15 shows a measurement of the time required for DAC A to reflect the change in NCO frequency from 10 MHz to 20 MHz after issuing SYSREF. Approximately 200 ns are required for the DAC output to reflect the change in frequency.

using-sysref-to-update-NCO-output-takes-approximately-200-ns.gifFigure 15. Using SYSREF to Update NCO Output Requires Approximately 200 ns to Update the NCO Output