In a typical OBC application, gate drivers are required to prevent unintended turn-on events and direct shoot-through in the high side and low side switches. UCC21330-Q1 is an isolated dual-channel gate driver with 4A peak-source and 6A peak-sink current to drive power MOSFET, SiC, GaN, and IGBT transistors.

The protection features of UCC21330-Q1 include resistor programmable dead time, disable feature to shut down both outputs simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5ns. All supplies have UVLO protection. The internal weak pull down on both INA and INB pin can verify the output will be low at default as a safe state. DIS pin disables both driver outputs if asserted high, enable both outputs if set low. In case of the detected failure state, a global DIS asserted by the microcontroller or other analog comparators disables all drivers at once.

To prevent direct shoot-through of the high side and low side FET during dynamic switching, the interlock function can be enabled by placing 0Ω to 150Ω resistor, or short DT pin to GND to have two outputs interlocked. If both inputs are high simultaneously, both outputs are immediately be set low. Figure 3-2 can illustrate this functionality.

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the dead time of the input signal is longer than the programmed dead time. Thus,

when INA goes high, this immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. INB’s own dead time is longer than the programmed dead time. Thus, when INB goes high, this

immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, INA immediately pulls

OUTB low and keeps OUTA low. After some time OUTB goes low and assigns the programmed dead time to

OUTA. OUTB is already low. After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, INB immediately pulls

OUTA low and keeps OUTB low. After some time OUTA goes low and assigns the programmed dead time to

OUTB. OUTA is already low. After the programmed dead time, OUTB is allowed to go high.

To verify robust and reliable operation of gate drivers, pay special attention to the minimum pulse width. The minimum input pulse width is dictated by the deglitch filter present in the driver IC, which determines the shortest pulse that will be transmitted to the output in an unloaded driver.

Under voltage lockout (UVLO) is implemented in gate drivers to monitor the gate voltage and prevent it from dropping below a specified threshold. The UVLO rating is an important consideration in high-power applications that use Si & SiC MOSFETs or IGBTs.

• UVLO is a key feature to verify the system is protected in case of a bias supply failure.
• High UVLO is required for SiC MOSFETs and IGBTs in high power applications due to the device characteristics and high-power system. The efficient switching of these devices is critical to prevent destruction or reduced lifetime.

For high switching frequency or hard-switching applications, to prevent false turn-on of the gate driver, miller clamp is preferred to increase overall system robustness. The UCC5350-Q1 is a single-channel, isolated gate driver with 10A source and 10A sink typical peak current, which has the option for Miller clamp or Split Outputs.

• Vds dv/dt results in current through Cgd, also known as the miller capacitance. This Miller current induces a voltage at the gate

• The Miller Clamp introduces a low-impedance path to bypass the Miller current and prevent false turn-on when the gate driver is OFF.

This single-channel gate driver integrates specific logic to prevent shoot through. Interlock can be achieved by simply connecting IN+ and IN- respectively into 1-ch devices. If both high-side and low-side gate drivers are sent an input high, the drivers disable the output to prevent shoot-through. The logic table is listed in Table 3-1.

If additional advanced protection feature is desired, UCC218200-Q1 is an isolated gate-driver with overcurrent and short circuit detection, controlled soft shutdown after a fault, fault reporting, active Miller clamp, input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness, output voltage gate monitoring, and built-in self-test during startup.

Output voltage gate monitor checks to make sure gate voltage reaches > VDD - 3V when PWM is high and < VEE + 3V when PWM is low.

• RDY is pulled low when a gate monitor fault is detected.
• OUT_FB on LV side provides real time feedback output.

During the initial startup the driver runs a series of checks to verify the following comparators are not stuck high or low:

• DESAT/OC.
• VCC, VDD, and VEE UVLO.
• VDD-3V and VEE+3V gate monitors.
• Miller Clamp Threshold.