ZHCSIQ7A august   2018  – december 2021 UCC28951

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 7.3.4  Soft-Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select FETs QE and QF
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 8.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
      1.      Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

QA, QB, QC, QD FET Selection

In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon are chosen for QA..QD.

The FET drain to source on resistance is:

Equation 46. GUID-EBE34EFA-FA89-4C8F-BD6D-DDB97947504F-low.gif

The FET Specified COSS is:

Equation 47. GUID-6A163B8E-6101-491B-9E7D-180958C34754-low.gif

The voltage across drain-to-source (VdsQA) where COSS was measured as a data sheet parameter:

Equation 48. GUID-59DAC91D-5D57-4E1D-B44B-D26E2AB33D33-low.gif

Calculate average Coss [2] using Equation 49:

Equation 49. GUID-15CA8282-CB1B-4DAB-9FD4-769167681A11-low.gif

The QA FET gate charge is:

Equation 50. GUID-FD9DCC8D-6DAB-4FD0-9ACE-BAA3BAA22E31-low.gif

The voltage applied to FET gate to activate FET is:

Equation 51. GUID-43082C08-745F-4C89-99A4-8856AD9596A1-low.gif

Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg) using Equation 52:

Equation 52. GUID-A3A0604E-A50D-4FBC-AA99-729E835ADFDA-low.gif

Recalculate the power budget using Equation 53:

Equation 53. GUID-746DD267-9CF2-451B-879C-99B31E538F08-low.gif