SLUSFW8 March   2025 UCC27624V

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Supply Current
      2. 6.3.2 Input Stage
      3. 6.3.3 Enable Function
      4. 6.3.4 Output Stage
      5. 6.3.5 Low Propagation Delays and Tightly Matched Outputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD and Undervoltage Lockout
        2. 7.2.2.2 Drive Current and Power Dissipation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • D|8
  • DGN|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.5 Electrical Characteristics

Unless otherwise noted, VDD = 12 V, TA = TJ = –40°C to 150°C, 1-µF capacitor from VDD to GND, no load on the output. Typical condition specifications are at 25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
BIAS CURRENTS
IVDDqVDD quiescent supply currentVINx = 3.3 V, VDD = 3.4 V, ENx = VDD300450μA
IVDDVDD static supply currentVINx = 3.3 V, ENx = VDD0.61.0mA
IVDDVDD static supply currentVINx = 0 V, ENx = VDD0.71.0mA
IVDDOVDD operating currentfSW = 1000 kHz, ENx = VDD, VINx = 0 V – 3.3 V PWM3.23.8mA
IDISVDD disable currentVINx = 3.3 V, ENx = 0 V0.81.1mA
UNDERVOLTAGE LOCKOUT (UVLO)
VVDD_ONVDD UVLO rising threshold8.08.59.0V
VVDD_OFFVDD UVLO falling threshold7.58.08.5V
VVDD_HYSVDD UVLO hysteresis0.5V
INPUT (INA, INB)
VINx_HInput signal high thresholdOutput High, ENx = HIGH1.822.3V
VINx_LInput signal low thresholdOutput Low, ENx = HIGH0.811.2V
VINx_HYSInput signal hysteresis1V
RINxINx pin pulldown resistorINx = 3.3 V120kΩ
ENABLE (ENA, ENB)
VENx_HEnable signal high thresholdOutput High, INx = HIGH1.822.3V
VENx_LEnable signal low thresholdOutput Low, INx = HIGH0.811.2V
VENx_HYSEnable signal hysteresis1V
RENxEN pin pullup resistanceENx = 0 V200kΩ
OUTPUTS (OUTA, OUTB)
ISRC(1)Peak output source currentVDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz5A
ISNK(1)Peak output sink currentVDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz–5A
ROH(2)Pullup resistanceIOUT = –50 mA, See Section 6.3.4.58.5Ω
ROLPulldown resistanceIOUT = 50 mA0.61.1Ω
(1) Parameter not tested in production.
(2) Output pullup resistance in this table is a DC measurement that measures resistance of PMOS structure only (not N-channel structure).