ZHCSK81A September   2019  – October 2020 TPS65296

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3 Control
      2. 7.3.2 Advanced Eco-mode Control
      3. 7.3.3 Soft Start and Prebiased Soft Start
      4. 7.3.4 Power Good
      5. 7.3.5 Overcurrent Protection and Undervoltage Protection
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Output Voltage Discharge
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
      2. 7.4.2 Output State Control
      3. 7.4.3 Output Sequence Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
          4. 8.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Support Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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8.1 Application Information

The TPS65296 device provides a complete power solution for LPDDR4/LPDDR4X memory system. Table 8-1 shows the power requirements for LPDDR4 and LPDDR4X.

Table 8-1 LPDDR4/LPDDR4X Application
VDD1VDD2VDDQ
LPDDR4YESYESNO(Leave this pin floating)
LPDDR4XYESYESYES

The schematic of Figure 8-1 shows a typical application for LPDDR4X. For VDD2 buck, the PVIN supports 4.5-V to 18-V input range with 1.1-V VDD2 output, the continuous current capability is 8 A. Usually the PVIN_VDD1 and VCC_5V can share one 5-V power input and supports 1.8-V VDD1 output with 1-A continuous current capability, and the PVIN_VDD1 can be lowered down to a 3.3-V power supply. The VLDOIN power input usually is connected to VDD2 output, while also it can be connected to external 1.1-V power supply input. The schematic of Figure 8-2 shows a typical application for LPDDR4. The TPS65296 can be used for LPDDR4 when connecting VDDQ_EN pin to GND to disable the LDO and leave VDDQ/VDDQSNS pin floating. It doesn't need input cap for VLDOIN and output cap for VDDQ compare with the application in LPDDR4X. While it also need to connect VLDOIN to VDD2 or external 1.1-V power supply for internal power supply.