ZHCSK81A September   2019  – October 2020 TPS65296

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3 Control
      2. 7.3.2 Advanced Eco-mode Control
      3. 7.3.3 Soft Start and Prebiased Soft Start
      4. 7.3.4 Power Good
      5. 7.3.5 Overcurrent Protection and Undervoltage Protection
      6. 7.3.6 Overvoltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Output Voltage Discharge
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation for VDD1 Buck and VDD2 Buck
      2. 7.4.2 Output State Control
      3. 7.4.3 Output Sequence Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
          4. 8.2.2.1.4 Bootstrap Capacitor and Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Support Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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7.4.2 Output State Control

The TPS65296 has two enable input pins (VDD_EN and VDDQ_EN) to provide simple control scheme of output state. All of VDD1, VDD2, and VDDQ are turned on at S0 state (VDD_EN=VDDQ_EN=high). In S3 state (VDDQ_EN=low, VDD_EN=high), VDD1 and VDD2 voltages are kept on while VDDQ is turned off and left at high impedance state (high-Z). The VDDQ output floats and does not source current in this state. In S4/S5 states (VDD_EN=VDDQ_EN =low), all of the three outputs are turned off and discharged to GND. Each state code represents as follows: S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF (see Table 7-1).

Table 7-1 VDDQ_EN and VDD_EN Control for Output State
STATEVDDQ_ENVDD_ENVDD1VDD2VDDQ
S0HIHIONONON
S3LOHIONONOFF (High-Z)
S5/S4LOLOOFF (discharge)OFF (discharge)OFF (discharge)