ZHCSPP3 July   2022 TPS563300

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode
      2. 7.3.2  Pulse Frequency Modulation
      3. 7.3.3  Voltage Reference
      4. 7.3.4  Output Voltage Setting
      5. 7.3.5  Enable and Adjusting Undervoltage Lockout
      6. 7.3.6  Minimum On Time, Minimum Off Time, and Frequency Foldback
      7. 7.3.7  Frequency Spread Spectrum
      8. 7.3.8  Overvoltage Protection
      9. 7.3.9  Overcurrent and Undervoltage Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes Overview
      2. 7.4.2 Heavy Load Operation
      3. 7.4.3 Light-Load Operation
      4. 7.4.4 Dropout Operation
      5. 7.4.5 Minimum On-Time Operation
      6. 7.4.6 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Bootstrap Capacitor Selection
        4. 8.2.2.4 Undervoltage Lockout Set Point
        5. 8.2.2.5 Output Inductor Selection
        6. 8.2.2.6 Output Capacitor Selection
        7. 8.2.2.7 Input Capacitor Selection
        8. 8.2.2.8 Feedforward Capacitor CFF Selection
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方产品免责声明
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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订购信息

8.2.2.6 Output Capacitor Selection

The device is designed to be used with a wide variety of LC filters, which is generally desired to use as little output capacitance as possible to keep cost and size down. The output capacitance, COUT, must be chosen with care since it directly affects the following specifications:

  • Steady state output voltage ripple
  • Loop stability
  • Output voltage overshoot and undershoot during load current transient

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the equivalent series resistance (ESR) of the output capacitors:

Equation 17. GUID-8930AE7F-ADCC-4D55-99AA-CBFA970A3944-low.gif

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 18. GUID-8ACF5EA9-7839-496F-A3D7-462D2E10D881-low.gif

K is the ripple ratio of the inductor current (ΔIL / IOUT_MAX). The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of the two peaks.

Output capacitance is usually limited by the load transient requirements rather than the output voltage ripple if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a large load step happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the converter usually needs eight or more clock cycles to regulate the inductor current equal to the new load level. The output capacitance must be large enough to supply the current difference for about eight clock cycles to maintain the output voltage within the specified range. Equation 19 shows the minimum output capacitance needed for specified VOUT overshoot and undershoot.

Equation 19. GUID-16207CAD-99E1-45E5-B3BF-1937F33795C7-low.gif

where

  • D is VOUT / VIN (duty cycle of steady state).
  • ΔVOUT is the output voltage change.
  • ΔIOUT is the output current change.

For this design example, the target output ripple is 30 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 30 mV and choose K = 0.4. Equation 17 yields ESR no larger than 25 mΩ and Equation 18 yields COUT no smaller than 10 μF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT < 5% × VOUT = 250 mV for an output current step of ΔIOUT = 1.5 A. COUT is calculated to be no smaller than 25 μF by Equation 19. In summary, the most stringent criterion for the output capacitor is 25 μF. Considering the ceramic capacitor has DC bias de-rating, it can be achieved with a bank of 2 × 22-μF, 35-V, ceramic capacitor C3216X5R1V226M160AC in the 1206 case size.

More output capacitors can be used to improve the load transient response. Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor can be placed in parallel with the ceramics to build up the required value of capacitance. When using a mixture of aluminum and ceramic capacitors, use the minimum recommended value of ceramics and add aluminum electrolytic capacitors as needed.

The recommendations given in Table 8-2 provide typical and minimum values of output capacitance for the given conditions. These values are the effective figures. If the minimum values are to be used, the design must be tested over all of the expected application conditions, including input voltage, output current, and ambient temperature. This testing must include both bode plot and load transient assessments. The maximum value of total output capacitance can be referred to the application note (COUT selection and CFF selection) on the TPS62933 product page. Large values of output capacitance can adversely affect the start-up behavior of the converter as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF to 100 nF can help reduce spikes on the output caused by inductor and board parasitics.

Table 8-2 shows the recommended LC combination.

Table 8-2 Recommended LC Combination
VOUT(V) RTOP(kΩ) RDOWN(kΩ) Typical Inductor L (μH) Typical Effective COUT (μF) Minimum Effective COUT (μF)
3.3 31.3 10.0 4.7 40 15
5 52.5 10.0 6.8 20 10
12 140.0 10.0 12 15 10