ZHCSUI2E May   2006  – January 2024 TPS28225

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Output Active Low
      3. 6.3.3 Enable/Power Good
      4. 6.3.4 3-State Input
        1. 6.3.4.1 TPS28225 3-State Exit Mode
        2. 6.3.4.2 External Resistor Interference
      5. 6.3.5 Bootstrap Diode
      6. 6.3.6 Upper and Lower Gate Drivers
      7. 6.3.7 Dead-Time Control
      8. 6.3.8 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Four Phases Driven by TPS28225 Driver
        2. 7.2.2.2 Switching The MOSFETs
        3. 7.2.2.3 List of Materials
      3. 7.2.3 Application Curves
    3. 7.3 System Examples
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

GUID-65A3654F-6F4A-40CB-BB56-1FF98B3F1A42-low.gif Figure 4-1 D Package8-Pin SOICTop View
GUID-B729F5D0-3F1D-48AB-A42C-DAF8EC07EE0E-low.gif Figure 4-2 DRB Package8-Pin VSONTop View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
SOIC VSON
BOOT 2 2 I/O Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the Phase pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET.
EN/PG 7 7 I/O Enable/power good input/output pin with 1-MΩ impedance. Connect this pin to High to enable and Low to disable the device. When disabled, the device draws less than 350-μA bias current. If the VDD is below UVLO threshold or over temperature shutdown occurs, this pin is internally pulled low.
GND 4 4 – Ground pin. All signals are referenced to this node.
LGATE 5 5 O Lower gate drive sink and source output. Connect to the gate of the low-side power N-Channel MOSFET.
PHASE 8 8 I Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver.
PWM 3 3 I The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the 3-state PWM Input section under DETAILED DESCRIPTION for further details. Connect this pin to the PWM output of the controller.
Thermal pad Exposed die pad – Connect directly to the GND for better thermal performance and EMI.
UGATE 1 1 O Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET.
VDD 6 6 I Connect this pin to a 5-V bias supply. Place a high quality bypass capacitor from this pin to GND.