The SN74LV8T245 is an octal bus transceiver with 3-state outputs. All eight channels are controlled by the direction (DIR) pin and output enable (OE) pin. Each transceiver includes one buffer oriented from Ax to Bx and one from Bx to Ax, with at least one output disabled at all times. The direction (DIR) pin controls which buffer is active. The buffer that is not active has the output placed into the high-impedance state.

The output enable (OE) controls all outputs in the device. When the OE pin is in the low state, the appropriate outputs as determined by the direction (DIR) pin are enabled. When the OE pin is in the high state, all outputs of the device are disabled. All disabled outputs are placed into the high-impedance state.

To ensure the high-impedance state during power up or power down, the OE pin should be tied to V_CC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver and the leakage of the pin as defined in the Electrical Characteristics table. Typically a 10-kΩ resistor will be sufficient.

The output level is referenced to the supply voltage (V_CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).