ZHCSI18A April   2018  – July 2018 OPA858


  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      高速飞行时间接收器
      2.      光电二极管电容与带宽和噪声
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input and ESD Protection
      2. 9.3.2 Feedback Pin
      3. 9.3.3 Wide Gain-Bandwidth Product
      4. 9.3.4 Slew Rate and Output Stage
      5. 9.3.5 Current Noise
    4. 9.4 Device Functional Modes
      1. 9.4.1 Split-Supply and Single-Supply Operation
      2. 9.4.2 Power-Down Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Using the OPA858 as a Transimpedance Amplifier
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 接收文档更新通知
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 术语表
  14. 14机械、封装和可订购信息


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Layout Guidelines

Achieving optimum performance with a high-frequency amplifier like the OPA858 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include:

  1. Minimize parasitic capacitance from the signal I/O pins to AC ground. Parasitic capacitance on the output and inverting input pins can cause instability. To reduce unwanted capacitance, TI recommends cutting out the power and ground traces underneath the signal input and output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is under 0.15 pF, consider using two series resistors, each of half the value of a single resistor in the feedback loop to minimize the parasitic capacitance from the resistor.
  2. Minimize the distance (less than 0.25") from the power-supply pins to high-frequency bypass capacitors. Use high quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times greater than the amplifiers maximum power supplies to ensure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must be used on the supply pins. These are placed further from the device and are shared among several devices in the same area of the PC board.
  3. Careful selection and placement of external components preserves the high-frequency performance of the OPA858 . Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting input termination resistors) close to the package. Even with a low parasitic capacitance shunting the external resistors, high resistor values create significant time constants that can degrade performance. When configuring the OPA858 as a voltage amplifier, keep resistor values as low as possible and consistent with load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power consumption because RF and RG become part of the output load network of the amplifier.